xref: /XiangShan/src/main/scala/xiangshan/Bundle.scala (revision 06a36b4fc9846f4cabc63aa8b4f243ab13e4d01b) 
1package xiangshan
2
3import chisel3._
4import chisel3.util._
5import bus.simplebus._
6
7// Fetch FetchWidth x 32-bit insts from Icache
8class FetchPacket extends XSBundle {
9  val instrs = Vec(FetchWidth, UInt(32.W))
10  val mask = UInt(FetchWidth.W)
11  val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
12}
13
14// Dequeue DecodeWidth insts from Ibuffer
15class CtrlFlow extends XSBundle {
16  val instr = UInt(32.W)
17  val pc = UInt(VAddrBits.W)
18  val exceptionVec = Vec(16, Bool())
19  val intrVec = Vec(12, Bool())
20  val isRVC = Bool()
21  val isBr = Bool()
22}
23
24// Decode DecodeWidth insts at Decode Stage
25class CtrlSignals extends XSBundle {
26  val src1Type, src2Type, src3Type = SrcType()
27  val lsrc1, lsrc2, lsrc3 = UInt(5.W)
28  val ldest = UInt(5.W)
29  val fuType = FuType()
30  val fuOpType = FuOpType()
31  val rfWen = Bool()
32  val fpWen = Bool()
33  val isXSTrap = Bool()
34  val noSpecExec = Bool()  // This inst can not be speculated
35  val isBlocked  = Bool()  // This inst requires pipeline to be blocked
36  val isRVF = Bool()
37  val imm = UInt(XLEN.W)
38}
39
40class CfCtrl extends XSBundle {
41  val cf = new CtrlFlow
42  val ctrl = new CtrlSignals
43  val brMask = UInt(BrqSize.W)
44  val brTag = UInt(BrTagWidth.W)
45}
46
47// CfCtrl -> MicroOp at Rename Stage
48class MicroOp extends CfCtrl {
49
50  val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
51  val src1State, src2State, src3State = SrcState()
52  val freelistAllocPtr = UInt(PhyRegIdxWidth.W)
53  val roqIdx = UInt(RoqIdxWidth.W)
54}
55
56class Redirect extends XSBundle {
57  val target = UInt(VAddrBits.W)
58  val brTag = UInt(BrTagWidth.W)
59  val isException = Bool()
60  val roqIdx = UInt(ExtendedRoqIdxWidth.W)
61  val freelistAllocPtr = UInt((PhyRegIdxWidth+1).W)
62}
63
64class Dp1ToDp2IO extends XSBundle {
65  val intDqToDp2 = Vec(IntDqDeqWidth, DecoupledIO(new MicroOp))
66  val fpDqToDp2 = Vec(FpDqDeqWidth, DecoupledIO(new MicroOp))
67  val lsDqToDp2 = Vec(LsDqDeqWidth, DecoupledIO(new MicroOp))
68}
69
70class DebugBundle extends XSBundle{
71  val isMMIO = Output(Bool())
72}
73
74class ExuInput extends XSBundle {
75  val uop = new MicroOp
76  val src1, src2, src3 = UInt(XLEN.W)
77}
78
79class ExuOutput extends XSBundle {
80  val uop = new MicroOp
81  val data = UInt(XLEN.W)
82  val redirect = Valid(new Redirect)
83  val debug = new DebugBundle
84}
85
86class ExuIO extends XSBundle {
87  val in = Flipped(DecoupledIO(new ExuInput))
88  val redirect = Flipped(ValidIO(new Redirect))
89  val out = DecoupledIO(new ExuOutput)
90
91  // for Lsu
92  val dmem = new SimpleBusUC
93}
94
95class RoqCommit extends XSBundle {
96  val uop = new MicroOp
97  val isWalk = Bool()
98}
99
100class FrontendToBackendIO extends XSBundle {
101  // to backend end
102  val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
103  // from backend
104  val redirect = Flipped(ValidIO(new Redirect))
105  val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred
106}