xref: /XiangShan/src/main/scala/xiangshan/Bundle.scala (revision 1e3fad102a1e42f73b646332d264923bfbe9c77e)
1*1e3fad10SLinJiaweipackage xiangshan
2*1e3fad10SLinJiawei
3*1e3fad10SLinJiaweiimport chisel3._
4*1e3fad10SLinJiawei
5*1e3fad10SLinJiaweiclass FetchPacket extends XSBundle {
6*1e3fad10SLinJiawei  val instrs = Vec(FetchWidth, UInt(32.W))
7*1e3fad10SLinJiawei  val mask = UInt(FetchWidth.W)
8*1e3fad10SLinJiawei  val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
9*1e3fad10SLinJiawei}
10*1e3fad10SLinJiawei
11*1e3fad10SLinJiaweiclass Redirect extends XSBundle {
12*1e3fad10SLinJiawei  val target = UInt(VAddrBits.W)
13*1e3fad10SLinJiawei}