1package utils 2 3import chisel3._ 4import chisel3.util._ 5 6class OverrideableQueue[T <: Data](gen: T, n: Int) extends Module { 7 val io = IO(new Bundle() { 8 val in = Flipped(ValidIO(gen)) 9 val out = Decoupled(gen) 10 }) 11 val entries = Seq.fill(n){ Reg(gen) } 12 val valids = Seq.fill(n){ RegInit(false.B) } 13 val rd_ptr = RegInit(0.U(log2Up(n).W)) 14 val wr_ptr = RegInit(0.U(log2Up(n).W)) 15 16 when(io.in.valid){ 17 wr_ptr := wr_ptr + 1.U 18 } 19 when(io.out.fire){ 20 rd_ptr := rd_ptr + 1.U 21 } 22 23 val w_mask = (0 until n).map(i => i.U === wr_ptr) 24 val r_mask = (0 until n).map(i => i.U === rd_ptr) 25 26 for((v, r) <- valids.zip(r_mask)){ 27 when(r && io.out.fire){ 28 v := false.B 29 } 30 } 31 32 for(((v, e), w) <- valids.zip(entries).zip(w_mask)){ 33 when(io.in.valid && w){ 34 v := true.B 35 e := io.in.bits 36 } 37 } 38 39 io.out.valid := Mux1H(r_mask, valids) 40 io.out.bits := Mux1H(r_mask, entries) 41} 42