1package utils 2 3import chisel3._ 4import chipsalliance.rocketchip.config.Parameters 5import chisel3.util.DecoupledIO 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import freechips.rocketchip.tilelink.{TLBundle, TLClientNode, TLIdentityNode, TLMasterParameters, TLMasterPortParameters} 8import xiangshan.HasXSLog 9 10class DataDontCareNode(a: Boolean = false, b: Boolean = false, c: Boolean = false, d: Boolean = false)(implicit p: Parameters) extends LazyModule { 11 12 val node = TLIdentityNode() 13 14 val n = TLClientNode(Seq(TLMasterPortParameters.v1( 15 Seq( 16 TLMasterParameters.v1("DataDontCareNode") 17 ) 18 ))) 19 20 lazy val module = new LazyModuleImp(this) with HasXSLog with HasTLDump{ 21 val (out, _) = node.out(0) 22 val (in, _) = node.in(0) 23 24 if (a) { 25 out.a.bits.data := DontCare 26 } 27 if (b) { 28 in.b.bits.data := DontCare 29 } 30 if (c) { 31 out.c.bits.data := DontCare 32 } 33 if (d) { 34 in.d.bits.data := DontCare 35 } 36 } 37} 38 39object DataDontCareNode { 40 def apply(a: Boolean = false, b: Boolean = false, c: Boolean = false, d: Boolean = false)(implicit p: Parameters): TLIdentityNode = { 41 val dataDontCareNode = LazyModule(new DataDontCareNode(a, b, c, d)) 42 dataDontCareNode.node 43 } 44} 45