xref: /XiangShan/src/main/scala/top/Top.scala (revision f973ab00f36a43196f948e67b30d0eff5b65d055) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import system._
24import device._
25import chisel3.stage.ChiselGeneratorAnnotation
26import chipsalliance.rocketchip.config._
27import device.{AXI4Plic, DebugModule, TLTimer}
28import freechips.rocketchip.diplomacy._
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.amba.axi4._
31import freechips.rocketchip.devices.tilelink._
32import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode
33import freechips.rocketchip.interrupts._
34import freechips.rocketchip.jtag.JTAGIO
35import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}
36import freechips.rocketchip.tilelink
37import freechips.rocketchip.util.{ElaborationArtefacts, HasRocketChipStageUtils, UIntToOH1}
38import huancun.debug.TLLogger
39import huancun.{HCCacheParamsKey, HuanCun}
40import freechips.rocketchip.devices.debug.{DebugIO, ResetCtrlIO}
41
42abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
43  with BindingScope
44{
45  val misc = LazyModule(new SoCMisc())
46  lazy val dts = DTS(bindingTree)
47  lazy val json = JSON(bindingTree)
48}
49
50class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
51{
52  ResourceBinding {
53    val width = ResourceInt(2)
54    val model = "freechips,rocketchip-unknown"
55    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
56    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
57    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
58    Resource(ResourceAnchors.root, "width").bind(width)
59    Resource(ResourceAnchors.soc, "width").bind(width)
60    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
61    def bindManagers(xbar: TLNexusNode) = {
62      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
63        manager.resources.foreach(r => r.bind(manager.toResource))
64      }
65    }
66    bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
67    bindManagers(misc.peripheralXbar.asInstanceOf[TLNexusNode])
68  }
69
70  println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
71
72  val core_with_l2 = soc.cores.map(coreParams =>
73    LazyModule(new XSTile()(p.alterPartial({
74      case XSCoreParamsKey => coreParams
75    })))
76  )
77
78  for (i <- 0 until NumCores) {
79    core_with_l2(i).clint_int_sink := misc.clint.intnode
80    core_with_l2(i).plic_int_sink := misc.plic.intnode
81    core_with_l2(i).debug_int_sink := misc.debugModule.debug.dmOuter.dmOuter.intnode
82    misc.plic.intnode := core_with_l2(i).beu_int_source
83    misc.peripheral_ports(i) := core_with_l2(i).uncache
84    misc.core_to_l3_ports(i) :=* core_with_l2(i).memory_port
85  }
86
87  val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
88    LazyModule(new HuanCun()(new Config((_, _, _) => {
89      case HCCacheParamsKey => l3param
90    })))
91  )
92
93  l3cacheOpt match {
94    case Some(l3) =>
95      misc.l3_out :*= l3.node :*= misc.l3_in
96    case None =>
97  }
98
99  lazy val module = new LazyRawModuleImp(this) {
100    ElaborationArtefacts.add("dts", dts)
101    ElaborationArtefacts.add("graphml", graphML)
102    ElaborationArtefacts.add("json", json)
103    ElaborationArtefacts.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
104
105    val dma = IO(Flipped(misc.dma.cloneType))
106    val peripheral = IO(misc.peripheral.cloneType)
107    val memory = IO(misc.memory.cloneType)
108
109    misc.dma <> dma
110    peripheral <> misc.peripheral
111    memory <> misc.memory
112
113    val io = IO(new Bundle {
114      val clock = Input(Bool())
115      val reset = Input(Bool())
116      val sram_config = Input(UInt(5.W))
117      val osc_clock = Input(Bool())
118      val pll_output = Output(UInt(14.W))
119      val extIntrs = Input(UInt(NrExtIntr.W))
120      val systemjtag = new Bundle {
121        val jtag = Flipped(new JTAGIO(hasTRSTn = false))
122        val reset = Input(Bool()) // No reset allowed on top
123        val mfr_id = Input(UInt(11.W))
124        val part_number = Input(UInt(16.W))
125        val version = Input(UInt(4.W))
126      }
127    })
128    io.pll_output := DontCare
129    dontTouch(io.sram_config)
130    dontTouch(io.osc_clock)
131    dontTouch(io.pll_output)
132    childClock := io.clock.asClock
133
134    withClockAndReset(childClock, io.reset) {
135      val resetGen = Module(new ResetGen(1, !debugOpts.FPGAPlatform))
136      resetGen.suggestName("top_reset_gen")
137      childReset := resetGen.io.out | misc.module.debug_module_io.debugIO.ndreset
138    }
139
140    withClockAndReset(childClock, childReset) {
141      misc.module.ext_intrs := io.extIntrs
142
143      for (i <- 0 until NumCores) {
144        val core_reset_gen = Module(new ResetGen(1, !debugOpts.FPGAPlatform))
145        core_reset_gen.suggestName(s"core_${i}_reset_gen")
146        core_with_l2(i).module.reset := core_reset_gen.io.out
147        core_with_l2(i).module.io.hartId := i.U
148      }
149
150      if (l3cacheOpt.nonEmpty) {
151        val l3_reset_gen = Module(new ResetGen(1, !debugOpts.FPGAPlatform))
152        l3_reset_gen.suggestName("l3_reset_gen")
153        l3cacheOpt.get.module.reset := l3_reset_gen.io.out
154      }
155
156      misc.module.debug_module_io.resetCtrl.hartIsInReset.foreach {x => x := childReset.asBool() }
157      misc.module.debug_module_io.clock := io.clock
158      misc.module.debug_module_io.reset := io.reset
159
160      misc.module.debug_module_io.debugIO.reset := io.systemjtag.reset // TODO: use synchronizer?
161      misc.module.debug_module_io.debugIO.clock := childClock
162      misc.module.debug_module_io.debugIO.dmactiveAck  := misc.module.debug_module_io.debugIO.dmactive // TODO: delay 3 cycles?
163      // jtag connector
164      misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
165        x.jtag <> io.systemjtag.jtag
166        x.reset  := io.systemjtag.reset
167        x.mfr_id := io.systemjtag.mfr_id
168        x.part_number := io.systemjtag.part_number
169        x.version := io.systemjtag.version
170      }
171    }
172  }
173}
174
175object TopMain extends App with HasRocketChipStageUtils {
176  override def main(args: Array[String]): Unit = {
177    val (config, firrtlOpts) = ArgParser.parse(args)
178    val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
179    XiangShanStage.execute(firrtlOpts, Seq(
180      ChiselGeneratorAnnotation(() => {
181        soc.module
182      })
183    ))
184    ElaborationArtefacts.files.foreach{ case (extension, contents) =>
185      writeOutputFile("./build", s"XSTop.${extension}", contents())
186    }
187  }
188}
189