xref: /XiangShan/src/main/scala/top/Top.scala (revision b1e920234888fd3e5463ceb2a99c9bdca087f585) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import huancun.PrefetchRecv
23import utility._
24import system._
25import device._
26import chisel3.stage.ChiselGeneratorAnnotation
27import org.chipsalliance.cde.config._
28import freechips.rocketchip.diplomacy._
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.jtag.JTAGIO
31import huancun.{HCCacheParamsKey, HuanCun, HCCacheParameters}
32
33abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
34  with BindingScope
35{
36  val misc = LazyModule(new SoCMisc())
37  lazy val dts = DTS(bindingTree)
38  lazy val json = JSON(bindingTree)
39}
40
41class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
42{
43  ResourceBinding {
44    val width = ResourceInt(2)
45    val model = "freechips,rocketchip-unknown"
46    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
47    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
48    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
49    Resource(ResourceAnchors.root, "width").bind(width)
50    Resource(ResourceAnchors.soc, "width").bind(width)
51    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
52    def bindManagers(xbar: TLNexusNode) = {
53      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
54        manager.resources.foreach(r => r.bind(manager.toResource))
55      }
56    }
57    bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
58    bindManagers(misc.peripheralXbar.asInstanceOf[TLNexusNode])
59  }
60
61  println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
62
63  val core_with_l2 = tiles.map(coreParams =>
64    LazyModule(new XSTile()(p.alterPartial({
65      case XSCoreParamsKey => coreParams
66    })))
67  )
68
69  val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
70    LazyModule(new HuanCun()(new Config((_, _, _) => {
71      case HCCacheParamsKey => l3param.copy(
72        hartIds = tiles.map(_.HartId),
73        FPGAPlatform = debugOpts.FPGAPlatform
74      )
75    })))
76  )
77
78  // recieve all prefetch req from cores
79  val memblock_pf_recv_nodes: Seq[Option[BundleBridgeSink[PrefetchRecv]]] = core_with_l2.map(_.core_l3_pf_port).map{
80    x => x.map(_ => BundleBridgeSink(Some(() => new PrefetchRecv)))
81  }
82
83  val l3_pf_sender_opt = soc.L3CacheParamsOpt.getOrElse(HCCacheParameters()).prefetch match {
84    case Some(pf) => Some(BundleBridgeSource(() => new PrefetchRecv))
85    case None => None
86  }
87
88  for (i <- 0 until NumCores) {
89    core_with_l2(i).clint_int_sink := misc.clint.intnode
90    core_with_l2(i).plic_int_sink :*= misc.plic.intnode
91    core_with_l2(i).debug_int_sink := misc.debugModule.debug.dmOuter.dmOuter.intnode
92    misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
93    misc.peripheral_ports(i) := core_with_l2(i).uncache
94    misc.core_to_l3_ports(i) :=* core_with_l2(i).memory_port
95    memblock_pf_recv_nodes(i).map(recv => {
96      println(s"Connecting Core_${i}'s L1 pf source to L3!")
97      recv := core_with_l2(i).core_l3_pf_port.get
98    })
99  }
100
101  l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar))
102  l3cacheOpt.map(_.intnode.map(int => {
103    misc.plic.intnode := IntBuffer() := int
104  }))
105
106  val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
107    l3cacheOpt.get.rst_nodes.get
108  } else {
109    core_with_l2.map(_ => BundleBridgeSource(() => Reset()))
110  }
111
112  core_rst_nodes.zip(core_with_l2.map(_.core_reset_sink)).foreach({
113    case (source, sink) =>  sink := source
114  })
115
116  l3cacheOpt match {
117    case Some(l3) =>
118      misc.l3_out :*= l3.node :*= misc.l3_banked_xbar
119      l3.pf_recv_node.map(recv => {
120        println("Connecting L1 prefetcher to L3!")
121        recv := l3_pf_sender_opt.get
122      })
123    case None =>
124  }
125
126  class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
127    FileRegisters.add("dts", dts)
128    FileRegisters.add("graphml", graphML)
129    FileRegisters.add("json", json)
130    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
131
132    val dma = IO(Flipped(misc.dma.cloneType))
133    val peripheral = IO(misc.peripheral.cloneType)
134    val memory = IO(misc.memory.cloneType)
135
136    misc.dma <> dma
137    peripheral <> misc.peripheral
138    memory <> misc.memory
139
140    val io = IO(new Bundle {
141      val clock = Input(Bool())
142      val reset = Input(AsyncReset())
143      val sram_config = Input(UInt(16.W))
144      val extIntrs = Input(UInt(NrExtIntr.W))
145      val pll0_lock = Input(Bool())
146      val pll0_ctrl = Output(Vec(6, UInt(32.W)))
147      val systemjtag = new Bundle {
148        val jtag = Flipped(new JTAGIO(hasTRSTn = false))
149        val reset = Input(AsyncReset()) // No reset allowed on top
150        val mfr_id = Input(UInt(11.W))
151        val part_number = Input(UInt(16.W))
152        val version = Input(UInt(4.W))
153      }
154      val debug_reset = Output(Bool())
155      val rtc_clock = Input(Bool())
156      val cacheable_check = new TLPMAIO()
157      val riscv_halt = Output(Vec(NumCores, Bool()))
158      val riscv_rst_vec = Input(Vec(NumCores, UInt(38.W)))
159    })
160
161    val reset_sync = withClockAndReset(io.clock.asClock, io.reset) { ResetGen() }
162    val jtag_reset_sync = withClockAndReset(io.systemjtag.jtag.TCK, io.systemjtag.reset) { ResetGen() }
163
164    // override LazyRawModuleImp's clock and reset
165    childClock := io.clock.asClock
166    childReset := reset_sync
167
168    // output
169    io.debug_reset := misc.module.debug_module_io.debugIO.ndreset
170
171    // input
172    dontTouch(dma)
173    dontTouch(io)
174    dontTouch(peripheral)
175    dontTouch(memory)
176    misc.module.ext_intrs := io.extIntrs
177    misc.module.rtc_clock := io.rtc_clock
178    misc.module.pll0_lock := io.pll0_lock
179    misc.module.cacheable_check <> io.cacheable_check
180
181    io.pll0_ctrl <> misc.module.pll0_ctrl
182
183    for ((core, i) <- core_with_l2.zipWithIndex) {
184      core.module.io.hartId := i.U
185      io.riscv_halt(i) := core.module.io.cpu_halt
186      core.module.io.reset_vector := io.riscv_rst_vec(i)
187    }
188
189    if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
190      // tie off core soft reset
191      for(node <- core_rst_nodes){
192        node.out.head._1 := false.B.asAsyncReset
193      }
194    }
195
196    l3cacheOpt match {
197      case Some(l3) =>
198        l3.pf_recv_node match {
199          case Some(recv) =>
200            l3_pf_sender_opt.get.out.head._1.addr_valid := VecInit(memblock_pf_recv_nodes.map(_.get.in.head._1.addr_valid)).asUInt.orR
201            for (i <- 0 until NumCores) {
202              when(memblock_pf_recv_nodes(i).get.in.head._1.addr_valid) {
203                l3_pf_sender_opt.get.out.head._1.addr := memblock_pf_recv_nodes(i).get.in.head._1.addr
204                l3_pf_sender_opt.get.out.head._1.l2_pf_en := memblock_pf_recv_nodes(i).get.in.head._1.l2_pf_en
205              }
206            }
207          case None =>
208        }
209        l3.module.io.debugTopDown.robHeadPaddr := core_with_l2.map(_.module.io.debugTopDown.robHeadPaddr)
210        core_with_l2.zip(l3.module.io.debugTopDown.addrMatch).foreach { case (tile, l3Match) => tile.module.io.debugTopDown.l3MissMatch := l3Match }
211      case None => core_with_l2.foreach(_.module.io.debugTopDown.l3MissMatch := false.B)
212    }
213
214    misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
215    misc.module.debug_module_io.clock := io.clock
216    misc.module.debug_module_io.reset := reset_sync
217
218    misc.module.debug_module_io.debugIO.reset := misc.module.reset
219    misc.module.debug_module_io.debugIO.clock := io.clock.asClock
220    // TODO: delay 3 cycles?
221    misc.module.debug_module_io.debugIO.dmactiveAck := misc.module.debug_module_io.debugIO.dmactive
222    // jtag connector
223    misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
224      x.jtag        <> io.systemjtag.jtag
225      x.reset       := jtag_reset_sync
226      x.mfr_id      := io.systemjtag.mfr_id
227      x.part_number := io.systemjtag.part_number
228      x.version     := io.systemjtag.version
229    }
230
231    withClockAndReset(io.clock.asClock, reset_sync) {
232      // Modules are reset one by one
233      // reset ----> SYNC --> {SoCMisc, L3 Cache, Cores}
234      val resetChain = Seq(Seq(misc.module) ++ l3cacheOpt.map(_.module) ++ core_with_l2.map(_.module))
235      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
236    }
237
238  }
239
240  lazy val module = new XSTopImp(this)
241}
242
243object TopMain extends App {
244  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
245
246  // tools: init to close dpi-c when in fpga
247  val envInFPGA = config(DebugOptionsKey).FPGAPlatform
248  val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
249  val enableConstantin = config(DebugOptionsKey).EnableConstantin
250  Constantin.init(enableConstantin && !envInFPGA)
251  ChiselDB.init(enableChiselDB && !envInFPGA)
252
253  val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
254  Generator.execute(firrtlOpts, soc.module, firtoolOpts)
255  FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.")
256}
257