xref: /XiangShan/src/main/scala/top/Top.scala (revision 887862dbb8debde8ab099befc426493834a69ee7) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9*          http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package top
19
20import chisel3._
21import chisel3.util._
22import chisel3.experimental.dataview._
23import difftest.DifftestModule
24import xiangshan._
25import utils._
26import huancun.{HCCacheParameters, HCCacheParamsKey, HuanCun, PrefetchRecv, TPmetaResp}
27import coupledL2.EnableCHI
28import openLLC.DummyLLC
29import utility._
30import system._
31import device._
32import chisel3.stage.ChiselGeneratorAnnotation
33import org.chipsalliance.cde.config._
34import freechips.rocketchip.diplomacy._
35import freechips.rocketchip.tile._
36import freechips.rocketchip.tilelink._
37import freechips.rocketchip.amba.axi4._
38import freechips.rocketchip.jtag.JTAGIO
39import chisel3.experimental.{annotate, ChiselAnnotation}
40import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
41
42abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
43  with BindingScope
44{
45  // val misc = LazyModule(new SoCMisc())
46  lazy val dts = DTS(bindingTree)
47  lazy val json = JSON(bindingTree)
48}
49
50class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
51{
52  val nocMisc = if (enableCHI) Some(LazyModule(new MemMisc())) else None
53  val socMisc = if (!enableCHI) Some(LazyModule(new SoCMisc())) else None
54  val misc: MemMisc = if (enableCHI) nocMisc.get else socMisc.get
55
56  ResourceBinding {
57    val width = ResourceInt(2)
58    val model = "xiangshan," + os.read(os.resource / "publishVersion")
59    val compatible = "freechips,rocketchip-unknown"
60    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
61    Resource(ResourceAnchors.root, "compat").bind(ResourceString(compatible + "-dev"))
62    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(compatible + "-soc"))
63    Resource(ResourceAnchors.root, "width").bind(width)
64    Resource(ResourceAnchors.soc, "width").bind(width)
65    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
66    def bindManagers(xbar: TLNexusNode) = {
67      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
68        manager.resources.foreach(r => r.bind(manager.toResource))
69      }
70    }
71    if (!enableCHI) {
72      bindManagers(misc.l3_xbar.get.asInstanceOf[TLNexusNode])
73      bindManagers(misc.peripheralXbar.get.asInstanceOf[TLNexusNode])
74    }
75  }
76
77  println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
78
79  val core_with_l2 = tiles.map(coreParams =>
80    LazyModule(new XSTile()(p.alter((site, here, up) => {
81      case XSCoreParamsKey => coreParams
82      case PerfCounterOptionsKey => up(PerfCounterOptionsKey).copy(perfDBHartID = coreParams.HartId)
83    })))
84  )
85
86  val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
87    LazyModule(new HuanCun()(new Config((_, _, _) => {
88      case HCCacheParamsKey => l3param.copy(
89        hartIds = tiles.map(_.HartId),
90        FPGAPlatform = debugOpts.FPGAPlatform
91      )
92      case MaxHartIdBits => p(MaxHartIdBits)
93      case LogUtilsOptionsKey => p(LogUtilsOptionsKey)
94      case PerfCounterOptionsKey => p(PerfCounterOptionsKey)
95    })))
96  )
97
98  val chi_dummyllc_opt = Option.when(enableCHI)(LazyModule(new DummyLLC(numRNs = NumCores)(p)))
99
100  // receive all prefetch req from cores
101  val memblock_pf_recv_nodes: Seq[Option[BundleBridgeSink[PrefetchRecv]]] = core_with_l2.map(_.core_l3_pf_port).map{
102    x => x.map(_ => BundleBridgeSink(Some(() => new PrefetchRecv)))
103  }
104
105  val l3_pf_sender_opt = soc.L3CacheParamsOpt.getOrElse(HCCacheParameters()).prefetch match {
106    case Some(pf) => Some(BundleBridgeSource(() => new PrefetchRecv))
107    case None => None
108  }
109
110  for (i <- 0 until NumCores) {
111    core_with_l2(i).clint_int_node := misc.clint.intnode
112    core_with_l2(i).plic_int_node :*= misc.plic.intnode
113    core_with_l2(i).debug_int_node := misc.debugModule.debug.dmOuter.dmOuter.intnode
114    misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
115    if (!enableCHI) {
116      misc.peripheral_ports.get(i) := core_with_l2(i).tl_uncache
117    }
118    core_with_l2(i).memory_port.foreach(port => (misc.core_to_l3_ports.get)(i) :=* port)
119    memblock_pf_recv_nodes(i).map(recv => {
120      println(s"Connecting Core_${i}'s L1 pf source to L3!")
121      recv := core_with_l2(i).core_l3_pf_port.get
122    })
123  }
124
125  l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar.get))
126  l3cacheOpt.map(_.intnode.map(int => {
127    misc.plic.intnode := IntBuffer() := int
128  }))
129
130  val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
131    l3cacheOpt.get.rst_nodes.get
132  } else {
133    core_with_l2.map(_ => BundleBridgeSource(() => Reset()))
134  }
135
136  core_rst_nodes.zip(core_with_l2.map(_.core_reset_sink)).foreach({
137    case (source, sink) =>  sink := source
138  })
139
140  l3cacheOpt match {
141    case Some(l3) =>
142      misc.l3_out :*= l3.node :*= misc.l3_banked_xbar.get
143      l3.pf_recv_node.map(recv => {
144        println("Connecting L1 prefetcher to L3!")
145        recv := l3_pf_sender_opt.get
146      })
147      l3.tpmeta_recv_node.foreach(recv => {
148        for ((core, i) <- core_with_l2.zipWithIndex) {
149          println(s"Connecting core_$i\'s L2 TPmeta request to L3!")
150          recv := core.core_l3_tpmeta_source_port.get
151        }
152      })
153      l3.tpmeta_send_node.foreach(send => {
154        val broadcast = LazyModule(new ValidIOBroadcast[TPmetaResp]())
155        broadcast.node := send
156        for ((core, i) <- core_with_l2.zipWithIndex) {
157          println(s"Connecting core_$i\'s L2 TPmeta response to L3!")
158          core.core_l3_tpmeta_sink_port.get := broadcast.node
159        }
160      })
161    case None =>
162  }
163
164  chi_dummyllc_opt match {
165    case Some(llc) =>
166      misc.soc_xbar.get := llc.axi4node
167    case None =>
168  }
169
170  class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
171    soc.XSTopPrefix.foreach { prefix =>
172      val mod = this.toNamed
173      annotate(new ChiselAnnotation {
174        def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
175      })
176    }
177
178    FileRegisters.add("dts", dts)
179    FileRegisters.add("graphml", graphML)
180    FileRegisters.add("json", json)
181    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
182
183    val dma = socMisc.map(m => IO(Flipped(new VerilogAXI4Record(m.dma.elts.head.params))))
184    val peripheral = IO(new VerilogAXI4Record(misc.peripheral.elts.head.params))
185    val memory = IO(new VerilogAXI4Record(misc.memory.elts.head.params))
186
187    socMisc match {
188      case Some(m) =>
189        m.dma.elements.head._2 <> dma.get.viewAs[AXI4Bundle]
190        dontTouch(dma.get)
191      case None =>
192    }
193
194    memory.viewAs[AXI4Bundle] <> misc.memory.elements.head._2
195    peripheral.viewAs[AXI4Bundle] <> misc.peripheral.elements.head._2
196
197    val io = IO(new Bundle {
198      val clock = Input(Bool())
199      val reset = Input(AsyncReset())
200      val sram_config = Input(UInt(16.W))
201      val extIntrs = Input(UInt(NrExtIntr.W))
202      val pll0_lock = Input(Bool())
203      val pll0_ctrl = Output(Vec(6, UInt(32.W)))
204      val systemjtag = new Bundle {
205        val jtag = Flipped(new JTAGIO(hasTRSTn = false))
206        val reset = Input(AsyncReset()) // No reset allowed on top
207        val mfr_id = Input(UInt(11.W))
208        val part_number = Input(UInt(16.W))
209        val version = Input(UInt(4.W))
210      }
211      val debug_reset = Output(Bool())
212      val rtc_clock = Input(Bool())
213      val cacheable_check = new TLPMAIO()
214      val riscv_halt = Output(Vec(NumCores, Bool()))
215      val riscv_rst_vec = Input(Vec(NumCores, UInt(soc.PAddrBits.W)))
216    })
217
218    val reset_sync = withClockAndReset(io.clock.asClock, io.reset) { ResetGen() }
219    val jtag_reset_sync = withClockAndReset(io.systemjtag.jtag.TCK, io.systemjtag.reset) { ResetGen() }
220
221    // override LazyRawModuleImp's clock and reset
222    childClock := io.clock.asClock
223    childReset := reset_sync
224
225    // output
226    io.debug_reset := misc.module.debug_module_io.debugIO.ndreset
227
228    // input
229    dontTouch(io)
230    dontTouch(memory)
231    misc.module.ext_intrs := io.extIntrs
232    misc.module.rtc_clock := io.rtc_clock
233    misc.module.pll0_lock := io.pll0_lock
234    misc.module.cacheable_check <> io.cacheable_check
235
236    io.pll0_ctrl <> misc.module.pll0_ctrl
237
238    val msiInfo = WireInit(0.U.asTypeOf(ValidIO(new MsiInfoBundle)))
239
240
241    for ((core, i) <- core_with_l2.zipWithIndex) {
242      core.module.io.hartId := i.U
243      core.module.io.msiInfo := msiInfo
244      core.module.io.clintTime := misc.module.clintTime
245      io.riscv_halt(i) := core.module.io.cpu_halt
246      core.module.io.reset_vector := io.riscv_rst_vec(i)
247      chi_dummyllc_opt.foreach { case llc =>
248        llc.module.io.rn(i) <> core.module.io.chi.get
249        core.module.io.nodeID.get := i.U // TODO
250      }
251    }
252
253    if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
254      // tie off core soft reset
255      for(node <- core_rst_nodes){
256        node.out.head._1 := false.B.asAsyncReset
257      }
258    }
259
260    l3cacheOpt match {
261      case Some(l3) =>
262        l3.pf_recv_node match {
263          case Some(recv) =>
264            l3_pf_sender_opt.get.out.head._1.addr_valid := VecInit(memblock_pf_recv_nodes.map(_.get.in.head._1.addr_valid)).asUInt.orR
265            for (i <- 0 until NumCores) {
266              when(memblock_pf_recv_nodes(i).get.in.head._1.addr_valid) {
267                l3_pf_sender_opt.get.out.head._1.addr := memblock_pf_recv_nodes(i).get.in.head._1.addr
268                l3_pf_sender_opt.get.out.head._1.l2_pf_en := memblock_pf_recv_nodes(i).get.in.head._1.l2_pf_en
269              }
270            }
271          case None =>
272        }
273        l3.module.io.debugTopDown.robHeadPaddr := core_with_l2.map(_.module.io.debugTopDown.robHeadPaddr)
274        core_with_l2.zip(l3.module.io.debugTopDown.addrMatch).foreach { case (tile, l3Match) => tile.module.io.debugTopDown.l3MissMatch := l3Match }
275      case None => core_with_l2.foreach(_.module.io.debugTopDown.l3MissMatch := false.B)
276    }
277
278    core_with_l2.foreach { case tile =>
279      tile.module.io.nodeID.foreach { case nodeID =>
280        nodeID := DontCare
281        dontTouch(nodeID)
282      }
283    }
284
285    misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
286    misc.module.debug_module_io.clock := io.clock
287    misc.module.debug_module_io.reset := reset_sync
288
289    misc.module.debug_module_io.debugIO.reset := misc.module.reset
290    misc.module.debug_module_io.debugIO.clock := io.clock.asClock
291    // TODO: delay 3 cycles?
292    misc.module.debug_module_io.debugIO.dmactiveAck := misc.module.debug_module_io.debugIO.dmactive
293    // jtag connector
294    misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
295      x.jtag        <> io.systemjtag.jtag
296      x.reset       := jtag_reset_sync
297      x.mfr_id      := io.systemjtag.mfr_id
298      x.part_number := io.systemjtag.part_number
299      x.version     := io.systemjtag.version
300    }
301
302    withClockAndReset(io.clock.asClock, reset_sync) {
303      // Modules are reset one by one
304      // reset ----> SYNC --> {SoCMisc, L3 Cache, Cores}
305      val resetChain = Seq(Seq(misc.module) ++ l3cacheOpt.map(_.module) ++ core_with_l2.map(_.module))
306      ResetGen(resetChain, reset_sync, !debugOpts.ResetGen)
307    }
308
309  }
310
311  lazy val module = new XSTopImp(this)
312}
313
314object TopMain extends App {
315  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
316
317  // tools: init to close dpi-c when in fpga
318  val envInFPGA = config(DebugOptionsKey).FPGAPlatform
319  val enableDifftest = config(DebugOptionsKey).EnableDifftest
320  val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
321  val enableConstantin = config(DebugOptionsKey).EnableConstantin
322  Constantin.init(enableConstantin && !envInFPGA)
323  ChiselDB.init(enableChiselDB && !envInFPGA)
324
325  val soc = if (config(SoCParamsKey).UseXSNoCTop)
326    DisableMonitors(p => LazyModule(new XSNoCTop()(p)))(config)
327  else
328    DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
329
330  Generator.execute(firrtlOpts, soc.module, firtoolOpts)
331
332  // generate difftest bundles (w/o DifftestTopIO)
333  if (enableDifftest) {
334    DifftestModule.finish("XiangShan", false)
335  }
336
337  FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.")
338}
339