xref: /XiangShan/src/main/scala/top/Top.scala (revision 7a2fc509e2d355879c4db3dc3f17a6ccacd3d09e) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import system._
24import device._
25import chisel3.stage.ChiselGeneratorAnnotation
26import chipsalliance.rocketchip.config._
27import freechips.rocketchip.diplomacy._
28import freechips.rocketchip.tilelink._
29import freechips.rocketchip.jtag.JTAGIO
30import freechips.rocketchip.util.{ElaborationArtefacts, HasRocketChipStageUtils, UIntToOH1}
31import huancun.{HCCacheParamsKey, HuanCun}
32
33abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
34  with BindingScope
35{
36  val misc = LazyModule(new SoCMisc())
37  lazy val dts = DTS(bindingTree)
38  lazy val json = JSON(bindingTree)
39}
40
41class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
42{
43  ResourceBinding {
44    val width = ResourceInt(2)
45    val model = "freechips,rocketchip-unknown"
46    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
47    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
48    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
49    Resource(ResourceAnchors.root, "width").bind(width)
50    Resource(ResourceAnchors.soc, "width").bind(width)
51    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
52    def bindManagers(xbar: TLNexusNode) = {
53      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
54        manager.resources.foreach(r => r.bind(manager.toResource))
55      }
56    }
57    bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
58    bindManagers(misc.peripheralXbar.asInstanceOf[TLNexusNode])
59  }
60
61  println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
62
63  val core_with_l2 = tiles.map(coreParams =>
64    LazyModule(new XSTile()(p.alterPartial({
65      case XSCoreParamsKey => coreParams
66    })))
67  )
68
69  val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
70    LazyModule(new HuanCun()(new Config((_, _, _) => {
71      case HCCacheParamsKey => l3param
72    })))
73  )
74
75  for (i <- 0 until NumCores) {
76    core_with_l2(i).clint_int_sink := misc.clint.intnode
77    core_with_l2(i).plic_int_sink :*= misc.plic.intnode
78    core_with_l2(i).debug_int_sink := misc.debugModule.debug.dmOuter.dmOuter.intnode
79    misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
80    misc.peripheral_ports(i) := core_with_l2(i).uncache
81    misc.core_to_l3_ports(i) :=* core_with_l2(i).memory_port
82  }
83
84  l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar))
85  l3cacheOpt.map(_.intnode.map(int => {
86    misc.plic.intnode := IntBuffer() := int
87  }))
88
89  val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
90    l3cacheOpt.get.rst_nodes.get
91  } else {
92    core_with_l2.map(_ => BundleBridgeSource(() => Bool()))
93  }
94
95  core_rst_nodes.zip(core_with_l2.map(_.core_reset_sink)).foreach({
96    case (source, sink) =>  sink := source
97  })
98
99  l3cacheOpt match {
100    case Some(l3) =>
101      misc.l3_out :*= l3.node :*= TLBuffer.chainNode(2) :*= misc.l3_banked_xbar
102    case None =>
103  }
104
105  lazy val module = new LazyRawModuleImp(this) {
106    ElaborationArtefacts.add("dts", dts)
107    ElaborationArtefacts.add("graphml", graphML)
108    ElaborationArtefacts.add("json", json)
109    ElaborationArtefacts.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
110
111    val dma = IO(Flipped(misc.dma.cloneType))
112    val peripheral = IO(misc.peripheral.cloneType)
113    val memory = IO(misc.memory.cloneType)
114
115    misc.dma <> dma
116    peripheral <> misc.peripheral
117    memory <> misc.memory
118
119    val io = IO(new Bundle {
120      val clock = Input(Bool())
121      val reset = Input(Bool())
122      val sram_config = Input(UInt(16.W))
123      val extIntrs = Input(UInt(NrExtIntr.W))
124      val pll0_lock = Input(Bool())
125      val pll0_ctrl = Output(Vec(6, UInt(32.W)))
126      val systemjtag = new Bundle {
127        val jtag = Flipped(new JTAGIO(hasTRSTn = false))
128        val reset = Input(Bool()) // No reset allowed on top
129        val mfr_id = Input(UInt(11.W))
130        val part_number = Input(UInt(16.W))
131        val version = Input(UInt(4.W))
132      }
133      val debug_reset = Output(Bool())
134      val cacheable_check = new TLPMAIO()
135      val riscv_halt = Output(Vec(NumCores, Bool()))
136      val riscv_rst_vec = Input(Vec(NumCores, UInt(38.W)))
137    })
138    // override LazyRawModuleImp's clock and reset
139    childClock := io.clock.asClock
140    childReset := io.reset
141
142    // output
143    io.debug_reset := misc.module.debug_module_io.debugIO.ndreset
144
145    // input
146    dontTouch(dma)
147    dontTouch(io)
148    dontTouch(peripheral)
149    dontTouch(memory)
150    misc.module.ext_intrs := io.extIntrs
151    misc.module.pll0_lock := io.pll0_lock
152    misc.module.cacheable_check <> io.cacheable_check
153
154    io.pll0_ctrl <> misc.module.pll0_ctrl
155
156    for ((core, i) <- core_with_l2.zipWithIndex) {
157      core.module.io.hartId := i.U
158      io.riscv_halt(i) := core.module.io.cpu_halt
159      core.module.io.reset_vector := io.riscv_rst_vec(i)
160    }
161
162    if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
163      // tie off core soft reset
164      for(node <- core_rst_nodes){
165        node.out.head._1 := false.B
166      }
167    }
168
169    misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
170    misc.module.debug_module_io.clock := io.clock
171    misc.module.debug_module_io.reset := io.reset
172
173    // TODO: use synchronizer?
174    misc.module.debug_module_io.debugIO.reset := io.systemjtag.reset
175    misc.module.debug_module_io.debugIO.clock := io.clock.asClock
176    // TODO: delay 3 cycles?
177    misc.module.debug_module_io.debugIO.dmactiveAck := misc.module.debug_module_io.debugIO.dmactive
178    // jtag connector
179    misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
180      x.jtag        <> io.systemjtag.jtag
181      x.reset       := io.systemjtag.reset
182      x.mfr_id      := io.systemjtag.mfr_id
183      x.part_number := io.systemjtag.part_number
184      x.version     := io.systemjtag.version
185    }
186
187    withClockAndReset(io.clock.asClock, io.reset) {
188      // Modules are reset one by one
189      // reset ----> SYNC --> {SoCMisc, L3 Cache, Cores}
190      val resetChain = Seq(Seq(misc.module) ++ l3cacheOpt.map(_.module) ++ core_with_l2.map(_.module))
191      ResetGen(resetChain, io.reset, !debugOpts.FPGAPlatform)
192    }
193
194  }
195}
196
197object TopMain extends App with HasRocketChipStageUtils {
198  override def main(args: Array[String]): Unit = {
199    val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args)
200    val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
201    Generator.execute(firrtlOpts, soc.module, firrtlComplier)
202    ElaborationArtefacts.files.foreach{ case (extension, contents) =>
203      writeOutputFile("./build", s"XSTop.${extension}", contents())
204    }
205  }
206}
207