xref: /XiangShan/src/main/scala/top/Top.scala (revision 4daa5bf3c3f27e7fd090866d52405b21e107eb8d) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import huancun.{HCCacheParameters, HCCacheParamsKey, HuanCun, PrefetchRecv, TPmetaResp}
24import utility._
25import system._
26import device._
27import chisel3.stage.ChiselGeneratorAnnotation
28import org.chipsalliance.cde.config._
29import freechips.rocketchip.diplomacy._
30import freechips.rocketchip.tile._
31import freechips.rocketchip.tilelink._
32import freechips.rocketchip.jtag.JTAGIO
33import chisel3.experimental.{annotate, ChiselAnnotation}
34import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
35
36abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
37  with BindingScope
38{
39  val misc = LazyModule(new SoCMisc())
40  lazy val dts = DTS(bindingTree)
41  lazy val json = JSON(bindingTree)
42}
43
44class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
45{
46  ResourceBinding {
47    val width = ResourceInt(2)
48    val model = "freechips,rocketchip-unknown"
49    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
50    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
51    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
52    Resource(ResourceAnchors.root, "width").bind(width)
53    Resource(ResourceAnchors.soc, "width").bind(width)
54    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
55    def bindManagers(xbar: TLNexusNode) = {
56      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
57        manager.resources.foreach(r => r.bind(manager.toResource))
58      }
59    }
60    bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
61    bindManagers(misc.peripheralXbar.asInstanceOf[TLNexusNode])
62  }
63
64  println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
65
66  val core_with_l2 = tiles.map(coreParams =>
67    LazyModule(new XSTile()(p.alterPartial({
68      case XSCoreParamsKey => coreParams
69    })))
70  )
71
72  val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
73    LazyModule(new HuanCun()(new Config((_, _, _) => {
74      case HCCacheParamsKey => l3param.copy(
75        hartIds = tiles.map(_.HartId),
76        FPGAPlatform = debugOpts.FPGAPlatform
77      )
78      case MaxHartIdBits => p(MaxHartIdBits)
79    })))
80  )
81
82  // recieve all prefetch req from cores
83  val memblock_pf_recv_nodes: Seq[Option[BundleBridgeSink[PrefetchRecv]]] = core_with_l2.map(_.core_l3_pf_port).map{
84    x => x.map(_ => BundleBridgeSink(Some(() => new PrefetchRecv)))
85  }
86
87  val l3_pf_sender_opt = soc.L3CacheParamsOpt.getOrElse(HCCacheParameters()).prefetch match {
88    case Some(pf) => Some(BundleBridgeSource(() => new PrefetchRecv))
89    case None => None
90  }
91
92  for (i <- 0 until NumCores) {
93    core_with_l2(i).clint_int_node := misc.clint.intnode
94    core_with_l2(i).plic_int_node :*= misc.plic.intnode
95    core_with_l2(i).debug_int_node := misc.debugModule.debug.dmOuter.dmOuter.intnode
96    misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
97    misc.peripheral_ports(i) := core_with_l2(i).uncache
98    misc.core_to_l3_ports(i) :=* core_with_l2(i).memory_port
99    memblock_pf_recv_nodes(i).map(recv => {
100      println(s"Connecting Core_${i}'s L1 pf source to L3!")
101      recv := core_with_l2(i).core_l3_pf_port.get
102    })
103  }
104
105  l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar))
106  l3cacheOpt.map(_.intnode.map(int => {
107    misc.plic.intnode := IntBuffer() := int
108  }))
109
110  val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
111    l3cacheOpt.get.rst_nodes.get
112  } else {
113    core_with_l2.map(_ => BundleBridgeSource(() => Reset()))
114  }
115
116  core_rst_nodes.zip(core_with_l2.map(_.core_reset_sink)).foreach({
117    case (source, sink) =>  sink := source
118  })
119
120  l3cacheOpt match {
121    case Some(l3) =>
122      misc.l3_out :*= l3.node :*= misc.l3_banked_xbar
123      l3.pf_recv_node.map(recv => {
124        println("Connecting L1 prefetcher to L3!")
125        recv := l3_pf_sender_opt.get
126      })
127      l3.tpmeta_recv_node.foreach(recv => {
128        for ((core, i) <- core_with_l2.zipWithIndex) {
129          println(s"Connecting core_$i\'s L2 TPmeta request to L3!")
130          recv := core.core_l3_tpmeta_source_port.get
131        }
132      })
133      l3.tpmeta_send_node.foreach(send => {
134        val broadcast = LazyModule(new ValidIOBroadcast[TPmetaResp]())
135        broadcast.node := send
136        for ((core, i) <- core_with_l2.zipWithIndex) {
137          println(s"Connecting core_$i\'s L2 TPmeta response to L3!")
138          core.core_l3_tpmeta_sink_port.get := broadcast.node
139        }
140      })
141    case None =>
142  }
143
144  class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
145    soc.XSTopPrefix.foreach { prefix =>
146      val mod = this.toNamed
147      annotate(new ChiselAnnotation {
148        def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
149      })
150    }
151
152    FileRegisters.add("dts", dts)
153    FileRegisters.add("graphml", graphML)
154    FileRegisters.add("json", json)
155    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
156
157    val dma = IO(Flipped(misc.dma.cloneType))
158    val peripheral = IO(misc.peripheral.cloneType)
159    val memory = IO(misc.memory.cloneType)
160
161    misc.dma <> dma
162    peripheral <> misc.peripheral
163    memory <> misc.memory
164
165    val io = IO(new Bundle {
166      val clock = Input(Bool())
167      val reset = Input(AsyncReset())
168      val sram_config = Input(UInt(16.W))
169      val extIntrs = Input(UInt(NrExtIntr.W))
170      val pll0_lock = Input(Bool())
171      val pll0_ctrl = Output(Vec(6, UInt(32.W)))
172      val systemjtag = new Bundle {
173        val jtag = Flipped(new JTAGIO(hasTRSTn = false))
174        val reset = Input(AsyncReset()) // No reset allowed on top
175        val mfr_id = Input(UInt(11.W))
176        val part_number = Input(UInt(16.W))
177        val version = Input(UInt(4.W))
178      }
179      val debug_reset = Output(Bool())
180      val rtc_clock = Input(Bool())
181      val cacheable_check = new TLPMAIO()
182      val riscv_halt = Output(Vec(NumCores, Bool()))
183      val riscv_rst_vec = Input(Vec(NumCores, UInt(38.W)))
184    })
185
186    val reset_sync = withClockAndReset(io.clock.asClock, io.reset) { ResetGen() }
187    val jtag_reset_sync = withClockAndReset(io.systemjtag.jtag.TCK, io.systemjtag.reset) { ResetGen() }
188
189    // override LazyRawModuleImp's clock and reset
190    childClock := io.clock.asClock
191    childReset := reset_sync
192
193    // output
194    io.debug_reset := misc.module.debug_module_io.debugIO.ndreset
195
196    // input
197    dontTouch(dma)
198    dontTouch(io)
199    dontTouch(peripheral)
200    dontTouch(memory)
201    misc.module.ext_intrs := io.extIntrs
202    misc.module.rtc_clock := io.rtc_clock
203    misc.module.pll0_lock := io.pll0_lock
204    misc.module.cacheable_check <> io.cacheable_check
205
206    io.pll0_ctrl <> misc.module.pll0_ctrl
207
208    for ((core, i) <- core_with_l2.zipWithIndex) {
209      core.module.io.hartId := i.U
210      io.riscv_halt(i) := core.module.io.cpu_halt
211      core.module.io.reset_vector := io.riscv_rst_vec(i)
212    }
213
214    if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
215      // tie off core soft reset
216      for(node <- core_rst_nodes){
217        node.out.head._1 := false.B.asAsyncReset
218      }
219    }
220
221    l3cacheOpt match {
222      case Some(l3) =>
223        l3.pf_recv_node match {
224          case Some(recv) =>
225            l3_pf_sender_opt.get.out.head._1.addr_valid := VecInit(memblock_pf_recv_nodes.map(_.get.in.head._1.addr_valid)).asUInt.orR
226            for (i <- 0 until NumCores) {
227              when(memblock_pf_recv_nodes(i).get.in.head._1.addr_valid) {
228                l3_pf_sender_opt.get.out.head._1.addr := memblock_pf_recv_nodes(i).get.in.head._1.addr
229                l3_pf_sender_opt.get.out.head._1.l2_pf_en := memblock_pf_recv_nodes(i).get.in.head._1.l2_pf_en
230              }
231            }
232          case None =>
233        }
234        l3.module.io.debugTopDown.robHeadPaddr := core_with_l2.map(_.module.io.debugTopDown.robHeadPaddr)
235        core_with_l2.zip(l3.module.io.debugTopDown.addrMatch).foreach { case (tile, l3Match) => tile.module.io.debugTopDown.l3MissMatch := l3Match }
236      case None => core_with_l2.foreach(_.module.io.debugTopDown.l3MissMatch := false.B)
237    }
238
239    misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
240    misc.module.debug_module_io.clock := io.clock
241    misc.module.debug_module_io.reset := reset_sync
242
243    misc.module.debug_module_io.debugIO.reset := misc.module.reset
244    misc.module.debug_module_io.debugIO.clock := io.clock.asClock
245    // TODO: delay 3 cycles?
246    misc.module.debug_module_io.debugIO.dmactiveAck := misc.module.debug_module_io.debugIO.dmactive
247    // jtag connector
248    misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
249      x.jtag        <> io.systemjtag.jtag
250      x.reset       := jtag_reset_sync
251      x.mfr_id      := io.systemjtag.mfr_id
252      x.part_number := io.systemjtag.part_number
253      x.version     := io.systemjtag.version
254    }
255
256    withClockAndReset(io.clock.asClock, reset_sync) {
257      // Modules are reset one by one
258      // reset ----> SYNC --> {SoCMisc, L3 Cache, Cores}
259      val resetChain = Seq(Seq(misc.module) ++ l3cacheOpt.map(_.module) ++ core_with_l2.map(_.module))
260      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
261    }
262
263  }
264
265  lazy val module = new XSTopImp(this)
266}
267
268object TopMain extends App {
269  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
270
271  // tools: init to close dpi-c when in fpga
272  val envInFPGA = config(DebugOptionsKey).FPGAPlatform
273  val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
274  val enableConstantin = config(DebugOptionsKey).EnableConstantin
275  Constantin.init(enableConstantin && !envInFPGA)
276  ChiselDB.init(enableChiselDB && !envInFPGA)
277
278  val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
279  Generator.execute(firrtlOpts, soc.module, firtoolOpts)
280  FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.")
281}
282