xref: /XiangShan/src/main/scala/top/Top.scala (revision 4b40434cb8e9fec610aad0fda0e437863b2716ec) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import huancun.{HCCacheParameters, HCCacheParamsKey, HuanCun, PrefetchRecv, TPmetaResp}
24import coupledL2.EnableCHI
25import utility._
26import system._
27import device._
28import chisel3.stage.ChiselGeneratorAnnotation
29import org.chipsalliance.cde.config._
30import freechips.rocketchip.diplomacy._
31import freechips.rocketchip.tile._
32import freechips.rocketchip.tilelink._
33import freechips.rocketchip.amba.axi4._
34import freechips.rocketchip.jtag.JTAGIO
35import chisel3.experimental.{annotate, ChiselAnnotation}
36import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
37
38abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
39  with BindingScope
40{
41  // val misc = LazyModule(new SoCMisc())
42  lazy val dts = DTS(bindingTree)
43  lazy val json = JSON(bindingTree)
44}
45
46class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
47{
48  val enableCHI = p(EnableCHI)
49
50  val nocMisc = if (enableCHI) Some(LazyModule(new MemMisc())) else None
51  val socMisc = if (!enableCHI) Some(LazyModule(new SoCMisc())) else None
52  val misc: MemMisc = if (enableCHI) nocMisc.get else socMisc.get
53
54  ResourceBinding {
55    val width = ResourceInt(2)
56    val model = "freechips,rocketchip-unknown"
57    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
58    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
59    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
60    Resource(ResourceAnchors.root, "width").bind(width)
61    Resource(ResourceAnchors.soc, "width").bind(width)
62    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
63    def bindManagers(xbar: TLNexusNode) = {
64      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
65        manager.resources.foreach(r => r.bind(manager.toResource))
66      }
67    }
68    bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
69    bindManagers(misc.peripheralXbar.asInstanceOf[TLNexusNode])
70  }
71
72  println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
73
74  val core_with_l2 = tiles.map(coreParams =>
75    LazyModule(new XSTile()(p.alterPartial({
76      case XSCoreParamsKey => coreParams
77    })))
78  )
79
80  val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
81    LazyModule(new HuanCun()(new Config((_, _, _) => {
82      case HCCacheParamsKey => l3param.copy(
83        hartIds = tiles.map(_.HartId),
84        FPGAPlatform = debugOpts.FPGAPlatform
85      )
86      case MaxHartIdBits => p(MaxHartIdBits)
87    })))
88  )
89
90  // recieve all prefetch req from cores
91  val memblock_pf_recv_nodes: Seq[Option[BundleBridgeSink[PrefetchRecv]]] = core_with_l2.map(_.core_l3_pf_port).map{
92    x => x.map(_ => BundleBridgeSink(Some(() => new PrefetchRecv)))
93  }
94
95  val l3_pf_sender_opt = soc.L3CacheParamsOpt.getOrElse(HCCacheParameters()).prefetch match {
96    case Some(pf) => Some(BundleBridgeSource(() => new PrefetchRecv))
97    case None => None
98  }
99
100  for (i <- 0 until NumCores) {
101    core_with_l2(i).clint_int_node := misc.clint.intnode
102    core_with_l2(i).plic_int_node :*= misc.plic.intnode
103    core_with_l2(i).debug_int_node := misc.debugModule.debug.dmOuter.dmOuter.intnode
104    misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
105    if (!enableCHI) {
106      misc.peripheral_ports(i) := core_with_l2(i).tl_uncache
107    } else {
108      // Make diplomacy happy
109      val clientParameters = TLMasterPortParameters.v1(
110        clients = Seq(TLMasterParameters.v1(
111          "uncache"
112        ))
113      )
114      val clientNode = TLClientNode(Seq(clientParameters))
115      misc.peripheral_ports(i) := clientNode
116    }
117    misc.core_to_l3_ports.foreach(port => port(i) :=* core_with_l2(i).memory_port.get)
118    memblock_pf_recv_nodes(i).map(recv => {
119      println(s"Connecting Core_${i}'s L1 pf source to L3!")
120      recv := core_with_l2(i).core_l3_pf_port.get
121    })
122  }
123
124  l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar))
125  l3cacheOpt.map(_.intnode.map(int => {
126    misc.plic.intnode := IntBuffer() := int
127  }))
128
129  val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
130    l3cacheOpt.get.rst_nodes.get
131  } else {
132    core_with_l2.map(_ => BundleBridgeSource(() => Reset()))
133  }
134
135  core_rst_nodes.zip(core_with_l2.map(_.core_reset_sink)).foreach({
136    case (source, sink) =>  sink := source
137  })
138
139  l3cacheOpt match {
140    case Some(l3) =>
141      misc.l3_out :*= l3.node :*= misc.l3_banked_xbar
142      l3.pf_recv_node.map(recv => {
143        println("Connecting L1 prefetcher to L3!")
144        recv := l3_pf_sender_opt.get
145      })
146      l3.tpmeta_recv_node.foreach(recv => {
147        for ((core, i) <- core_with_l2.zipWithIndex) {
148          println(s"Connecting core_$i\'s L2 TPmeta request to L3!")
149          recv := core.core_l3_tpmeta_source_port.get
150        }
151      })
152      l3.tpmeta_send_node.foreach(send => {
153        val broadcast = LazyModule(new ValidIOBroadcast[TPmetaResp]())
154        broadcast.node := send
155        for ((core, i) <- core_with_l2.zipWithIndex) {
156          println(s"Connecting core_$i\'s L2 TPmeta response to L3!")
157          core.core_l3_tpmeta_sink_port.get := broadcast.node
158        }
159      })
160    case None =>
161  }
162
163  class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
164    soc.XSTopPrefix.foreach { prefix =>
165      val mod = this.toNamed
166      annotate(new ChiselAnnotation {
167        def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
168      })
169    }
170
171    FileRegisters.add("dts", dts)
172    FileRegisters.add("graphml", graphML)
173    FileRegisters.add("json", json)
174    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
175
176    val dma = socMisc.map(m => IO(Flipped(m.dma.cloneType)))
177    val peripheral = socMisc.map(m => IO(m.peripheral.cloneType))
178    val memory = IO(misc.memory.cloneType)
179
180    socMisc match {
181      case Some(m) =>
182        m.dma <> dma.get
183        peripheral.get <> m.peripheral
184        dontTouch(dma.get)
185        dontTouch(peripheral.get)
186      case None =>
187    }
188
189    memory <> misc.memory
190
191    val io = IO(new Bundle {
192      val clock = Input(Bool())
193      val reset = Input(AsyncReset())
194      val sram_config = Input(UInt(16.W))
195      val extIntrs = Input(UInt(NrExtIntr.W))
196      val pll0_lock = Input(Bool())
197      val pll0_ctrl = Output(Vec(6, UInt(32.W)))
198      val systemjtag = new Bundle {
199        val jtag = Flipped(new JTAGIO(hasTRSTn = false))
200        val reset = Input(AsyncReset()) // No reset allowed on top
201        val mfr_id = Input(UInt(11.W))
202        val part_number = Input(UInt(16.W))
203        val version = Input(UInt(4.W))
204      }
205      val debug_reset = Output(Bool())
206      val rtc_clock = Input(Bool())
207      val cacheable_check = new TLPMAIO()
208      val riscv_halt = Output(Vec(NumCores, Bool()))
209      val riscv_rst_vec = Input(Vec(NumCores, UInt(38.W)))
210    })
211
212    val reset_sync = withClockAndReset(io.clock.asClock, io.reset) { ResetGen() }
213    val jtag_reset_sync = withClockAndReset(io.systemjtag.jtag.TCK, io.systemjtag.reset) { ResetGen() }
214
215    // override LazyRawModuleImp's clock and reset
216    childClock := io.clock.asClock
217    childReset := reset_sync
218
219    // output
220    io.debug_reset := misc.module.debug_module_io.debugIO.ndreset
221
222    // input
223    dontTouch(io)
224    dontTouch(memory)
225    misc.module.ext_intrs := io.extIntrs
226    misc.module.rtc_clock := io.rtc_clock
227    misc.module.pll0_lock := io.pll0_lock
228    misc.module.cacheable_check <> io.cacheable_check
229
230    io.pll0_ctrl <> misc.module.pll0_ctrl
231
232    for ((core, i) <- core_with_l2.zipWithIndex) {
233      core.module.io.hartId := i.U
234      io.riscv_halt(i) := core.module.io.cpu_halt
235      core.module.io.reset_vector := io.riscv_rst_vec(i)
236    }
237
238    if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
239      // tie off core soft reset
240      for(node <- core_rst_nodes){
241        node.out.head._1 := false.B.asAsyncReset
242      }
243    }
244
245    l3cacheOpt match {
246      case Some(l3) =>
247        l3.pf_recv_node match {
248          case Some(recv) =>
249            l3_pf_sender_opt.get.out.head._1.addr_valid := VecInit(memblock_pf_recv_nodes.map(_.get.in.head._1.addr_valid)).asUInt.orR
250            for (i <- 0 until NumCores) {
251              when(memblock_pf_recv_nodes(i).get.in.head._1.addr_valid) {
252                l3_pf_sender_opt.get.out.head._1.addr := memblock_pf_recv_nodes(i).get.in.head._1.addr
253                l3_pf_sender_opt.get.out.head._1.l2_pf_en := memblock_pf_recv_nodes(i).get.in.head._1.l2_pf_en
254              }
255            }
256          case None =>
257        }
258        l3.module.io.debugTopDown.robHeadPaddr := core_with_l2.map(_.module.io.debugTopDown.robHeadPaddr)
259        core_with_l2.zip(l3.module.io.debugTopDown.addrMatch).foreach { case (tile, l3Match) => tile.module.io.debugTopDown.l3MissMatch := l3Match }
260      case None => core_with_l2.foreach(_.module.io.debugTopDown.l3MissMatch := false.B)
261    }
262
263    core_with_l2.foreach { case tile =>
264      tile.module.io.chi.foreach { case chi_port =>
265        chi_port <> DontCare
266        dontTouch(chi_port)
267      }
268      tile.module.io.nodeID.foreach { case nodeID =>
269        nodeID := DontCare
270        dontTouch(nodeID)
271      }
272    }
273
274    misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
275    misc.module.debug_module_io.clock := io.clock
276    misc.module.debug_module_io.reset := reset_sync
277
278    misc.module.debug_module_io.debugIO.reset := misc.module.reset
279    misc.module.debug_module_io.debugIO.clock := io.clock.asClock
280    // TODO: delay 3 cycles?
281    misc.module.debug_module_io.debugIO.dmactiveAck := misc.module.debug_module_io.debugIO.dmactive
282    // jtag connector
283    misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
284      x.jtag        <> io.systemjtag.jtag
285      x.reset       := jtag_reset_sync
286      x.mfr_id      := io.systemjtag.mfr_id
287      x.part_number := io.systemjtag.part_number
288      x.version     := io.systemjtag.version
289    }
290
291    withClockAndReset(io.clock.asClock, reset_sync) {
292      // Modules are reset one by one
293      // reset ----> SYNC --> {SoCMisc, L3 Cache, Cores}
294      val resetChain = Seq(Seq(misc.module) ++ l3cacheOpt.map(_.module) ++ core_with_l2.map(_.module))
295      ResetGen(resetChain, reset_sync, !debugOpts.ResetGen)
296    }
297
298  }
299
300  lazy val module = new XSTopImp(this)
301}
302
303object TopMain extends App {
304  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
305
306  // tools: init to close dpi-c when in fpga
307  val envInFPGA = config(DebugOptionsKey).FPGAPlatform
308  val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
309  val enableConstantin = config(DebugOptionsKey).EnableConstantin
310  Constantin.init(enableConstantin && !envInFPGA)
311  ChiselDB.init(enableChiselDB && !envInFPGA)
312
313  val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
314  Generator.execute(firrtlOpts, soc.module, firtoolOpts)
315  FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.")
316}
317