xref: /XiangShan/src/main/scala/top/Top.scala (revision 2993c5ecece73b73073301e23435ca1b763d0b5f) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9*          http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package top
19
20import chisel3._
21import chisel3.util._
22import chisel3.experimental.dataview._
23import difftest.DifftestModule
24import xiangshan._
25import utils._
26import huancun.{HCCacheParameters, HCCacheParamsKey, HuanCun, PrefetchRecv, TPmetaResp}
27import coupledL2.EnableCHI
28import utility._
29import system._
30import device._
31import chisel3.stage.ChiselGeneratorAnnotation
32import org.chipsalliance.cde.config._
33import freechips.rocketchip.diplomacy._
34import freechips.rocketchip.tile._
35import freechips.rocketchip.tilelink._
36import freechips.rocketchip.amba.axi4._
37import freechips.rocketchip.jtag.JTAGIO
38import chisel3.experimental.{annotate, ChiselAnnotation}
39import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
40
41abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
42  with BindingScope
43{
44  // val misc = LazyModule(new SoCMisc())
45  lazy val dts = DTS(bindingTree)
46  lazy val json = JSON(bindingTree)
47}
48
49class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
50{
51  val enableCHI = p(EnableCHI)
52
53  val nocMisc = if (enableCHI) Some(LazyModule(new MemMisc())) else None
54  val socMisc = if (!enableCHI) Some(LazyModule(new SoCMisc())) else None
55  val misc: MemMisc = if (enableCHI) nocMisc.get else socMisc.get
56
57  ResourceBinding {
58    val width = ResourceInt(2)
59    val model = "freechips,rocketchip-unknown"
60    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
61    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
62    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
63    Resource(ResourceAnchors.root, "width").bind(width)
64    Resource(ResourceAnchors.soc, "width").bind(width)
65    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
66    def bindManagers(xbar: TLNexusNode) = {
67      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
68        manager.resources.foreach(r => r.bind(manager.toResource))
69      }
70    }
71    bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
72    bindManagers(misc.peripheralXbar.asInstanceOf[TLNexusNode])
73  }
74
75  println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
76
77  val core_with_l2 = tiles.map(coreParams =>
78    LazyModule(new XSTile()(p.alterPartial({
79      case XSCoreParamsKey => coreParams
80    })))
81  )
82
83  val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
84    LazyModule(new HuanCun()(new Config((_, _, _) => {
85      case HCCacheParamsKey => l3param.copy(
86        hartIds = tiles.map(_.HartId),
87        FPGAPlatform = debugOpts.FPGAPlatform
88      )
89      case MaxHartIdBits => p(MaxHartIdBits)
90    })))
91  )
92
93  // recieve all prefetch req from cores
94  val memblock_pf_recv_nodes: Seq[Option[BundleBridgeSink[PrefetchRecv]]] = core_with_l2.map(_.core_l3_pf_port).map{
95    x => x.map(_ => BundleBridgeSink(Some(() => new PrefetchRecv)))
96  }
97
98  val l3_pf_sender_opt = soc.L3CacheParamsOpt.getOrElse(HCCacheParameters()).prefetch match {
99    case Some(pf) => Some(BundleBridgeSource(() => new PrefetchRecv))
100    case None => None
101  }
102
103  for (i <- 0 until NumCores) {
104    core_with_l2(i).clint_int_node := misc.clint.intnode
105    core_with_l2(i).plic_int_node :*= misc.plic.intnode
106    core_with_l2(i).debug_int_node := misc.debugModule.debug.dmOuter.dmOuter.intnode
107    misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
108    if (!enableCHI) {
109      misc.peripheral_ports(i) := core_with_l2(i).tl_uncache
110    } else {
111      // Make diplomacy happy
112      val clientParameters = TLMasterPortParameters.v1(
113        clients = Seq(TLMasterParameters.v1(
114          "uncache"
115        ))
116      )
117      val clientNode = TLClientNode(Seq(clientParameters))
118      misc.peripheral_ports(i) := clientNode
119    }
120    misc.core_to_l3_ports.foreach(port => port(i) :=* core_with_l2(i).memory_port.get)
121    memblock_pf_recv_nodes(i).map(recv => {
122      println(s"Connecting Core_${i}'s L1 pf source to L3!")
123      recv := core_with_l2(i).core_l3_pf_port.get
124    })
125  }
126
127  l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar))
128  l3cacheOpt.map(_.intnode.map(int => {
129    misc.plic.intnode := IntBuffer() := int
130  }))
131
132  val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
133    l3cacheOpt.get.rst_nodes.get
134  } else {
135    core_with_l2.map(_ => BundleBridgeSource(() => Reset()))
136  }
137
138  core_rst_nodes.zip(core_with_l2.map(_.core_reset_sink)).foreach({
139    case (source, sink) =>  sink := source
140  })
141
142  l3cacheOpt match {
143    case Some(l3) =>
144      misc.l3_out :*= l3.node :*= misc.l3_banked_xbar
145      l3.pf_recv_node.map(recv => {
146        println("Connecting L1 prefetcher to L3!")
147        recv := l3_pf_sender_opt.get
148      })
149      l3.tpmeta_recv_node.foreach(recv => {
150        for ((core, i) <- core_with_l2.zipWithIndex) {
151          println(s"Connecting core_$i\'s L2 TPmeta request to L3!")
152          recv := core.core_l3_tpmeta_source_port.get
153        }
154      })
155      l3.tpmeta_send_node.foreach(send => {
156        val broadcast = LazyModule(new ValidIOBroadcast[TPmetaResp]())
157        broadcast.node := send
158        for ((core, i) <- core_with_l2.zipWithIndex) {
159          println(s"Connecting core_$i\'s L2 TPmeta response to L3!")
160          core.core_l3_tpmeta_sink_port.get := broadcast.node
161        }
162      })
163    case None =>
164  }
165
166  class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
167    soc.XSTopPrefix.foreach { prefix =>
168      val mod = this.toNamed
169      annotate(new ChiselAnnotation {
170        def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
171      })
172    }
173
174    FileRegisters.add("dts", dts)
175    FileRegisters.add("graphml", graphML)
176    FileRegisters.add("json", json)
177    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
178
179    val dma = socMisc.map(m => IO(Flipped(new VerilogAXI4Record(m.dma.elts.head.params))))
180    val peripheral = socMisc.map(m => IO(new VerilogAXI4Record(m.peripheral.elts.head.params)))
181    val memory = IO(new VerilogAXI4Record(misc.memory.elts.head.params))
182
183    socMisc match {
184      case Some(m) =>
185        m.dma.elements.head._2 <> dma.get.viewAs[AXI4Bundle]
186        peripheral.get.viewAs[AXI4Bundle] <> m.peripheral.elements.head._2
187        dontTouch(dma.get)
188        dontTouch(peripheral.get)
189      case None =>
190    }
191
192    memory.viewAs[AXI4Bundle] <> misc.memory.elements.head._2
193
194    val io = IO(new Bundle {
195      val clock = Input(Bool())
196      val reset = Input(AsyncReset())
197      val sram_config = Input(UInt(16.W))
198      val extIntrs = Input(UInt(NrExtIntr.W))
199      val pll0_lock = Input(Bool())
200      val pll0_ctrl = Output(Vec(6, UInt(32.W)))
201      val systemjtag = new Bundle {
202        val jtag = Flipped(new JTAGIO(hasTRSTn = false))
203        val reset = Input(AsyncReset()) // No reset allowed on top
204        val mfr_id = Input(UInt(11.W))
205        val part_number = Input(UInt(16.W))
206        val version = Input(UInt(4.W))
207      }
208      val debug_reset = Output(Bool())
209      val rtc_clock = Input(Bool())
210      val cacheable_check = new TLPMAIO()
211      val riscv_halt = Output(Vec(NumCores, Bool()))
212      val riscv_rst_vec = Input(Vec(NumCores, UInt(38.W)))
213    })
214
215    val reset_sync = withClockAndReset(io.clock.asClock, io.reset) { ResetGen() }
216    val jtag_reset_sync = withClockAndReset(io.systemjtag.jtag.TCK, io.systemjtag.reset) { ResetGen() }
217
218    // override LazyRawModuleImp's clock and reset
219    childClock := io.clock.asClock
220    childReset := reset_sync
221
222    // output
223    io.debug_reset := misc.module.debug_module_io.debugIO.ndreset
224
225    // input
226    dontTouch(io)
227    dontTouch(memory)
228    misc.module.ext_intrs := io.extIntrs
229    misc.module.rtc_clock := io.rtc_clock
230    misc.module.pll0_lock := io.pll0_lock
231    misc.module.cacheable_check <> io.cacheable_check
232
233    io.pll0_ctrl <> misc.module.pll0_ctrl
234
235    for ((core, i) <- core_with_l2.zipWithIndex) {
236      core.module.io.hartId := i.U
237      io.riscv_halt(i) := core.module.io.cpu_halt
238      core.module.io.reset_vector := io.riscv_rst_vec(i)
239    }
240
241    if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
242      // tie off core soft reset
243      for(node <- core_rst_nodes){
244        node.out.head._1 := false.B.asAsyncReset
245      }
246    }
247
248    l3cacheOpt match {
249      case Some(l3) =>
250        l3.pf_recv_node match {
251          case Some(recv) =>
252            l3_pf_sender_opt.get.out.head._1.addr_valid := VecInit(memblock_pf_recv_nodes.map(_.get.in.head._1.addr_valid)).asUInt.orR
253            for (i <- 0 until NumCores) {
254              when(memblock_pf_recv_nodes(i).get.in.head._1.addr_valid) {
255                l3_pf_sender_opt.get.out.head._1.addr := memblock_pf_recv_nodes(i).get.in.head._1.addr
256                l3_pf_sender_opt.get.out.head._1.l2_pf_en := memblock_pf_recv_nodes(i).get.in.head._1.l2_pf_en
257              }
258            }
259          case None =>
260        }
261        l3.module.io.debugTopDown.robHeadPaddr := core_with_l2.map(_.module.io.debugTopDown.robHeadPaddr)
262        core_with_l2.zip(l3.module.io.debugTopDown.addrMatch).foreach { case (tile, l3Match) => tile.module.io.debugTopDown.l3MissMatch := l3Match }
263      case None => core_with_l2.foreach(_.module.io.debugTopDown.l3MissMatch := false.B)
264    }
265
266    core_with_l2.foreach { case tile =>
267      tile.module.io.chi.foreach { case chi_port =>
268        chi_port <> DontCare
269        dontTouch(chi_port)
270      }
271      tile.module.io.nodeID.foreach { case nodeID =>
272        nodeID := DontCare
273        dontTouch(nodeID)
274      }
275    }
276
277    misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
278    misc.module.debug_module_io.clock := io.clock
279    misc.module.debug_module_io.reset := reset_sync
280
281    misc.module.debug_module_io.debugIO.reset := misc.module.reset
282    misc.module.debug_module_io.debugIO.clock := io.clock.asClock
283    // TODO: delay 3 cycles?
284    misc.module.debug_module_io.debugIO.dmactiveAck := misc.module.debug_module_io.debugIO.dmactive
285    // jtag connector
286    misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
287      x.jtag        <> io.systemjtag.jtag
288      x.reset       := jtag_reset_sync
289      x.mfr_id      := io.systemjtag.mfr_id
290      x.part_number := io.systemjtag.part_number
291      x.version     := io.systemjtag.version
292    }
293
294    withClockAndReset(io.clock.asClock, reset_sync) {
295      // Modules are reset one by one
296      // reset ----> SYNC --> {SoCMisc, L3 Cache, Cores}
297      val resetChain = Seq(Seq(misc.module) ++ l3cacheOpt.map(_.module) ++ core_with_l2.map(_.module))
298      ResetGen(resetChain, reset_sync, !debugOpts.ResetGen)
299    }
300
301  }
302
303  lazy val module = new XSTopImp(this)
304}
305
306object TopMain extends App {
307  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
308
309  // tools: init to close dpi-c when in fpga
310  val envInFPGA = config(DebugOptionsKey).FPGAPlatform
311  val enableDifftest = config(DebugOptionsKey).EnableDifftest
312  val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
313  val enableConstantin = config(DebugOptionsKey).EnableConstantin
314  Constantin.init(enableConstantin && !envInFPGA)
315  ChiselDB.init(enableChiselDB && !envInFPGA)
316
317  val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
318  Generator.execute(firrtlOpts, soc.module, firtoolOpts)
319
320  // generate difftest bundles (w/o DifftestTopIO)
321  if (enableDifftest) {
322    DifftestModule.finish("XiangShan", false)
323  }
324
325  FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.")
326}
327