xref: /XiangShan/src/main/scala/top/Top.scala (revision 195ef4a53ab54326d879e884c4e1568f424f2668) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import difftest.DifftestModule
22import xiangshan._
23import utils._
24import huancun.{HCCacheParameters, HCCacheParamsKey, HuanCun, PrefetchRecv, TPmetaResp}
25import coupledL2.EnableCHI
26import utility._
27import system._
28import device._
29import chisel3.stage.ChiselGeneratorAnnotation
30import org.chipsalliance.cde.config._
31import freechips.rocketchip.diplomacy._
32import freechips.rocketchip.tile._
33import freechips.rocketchip.tilelink._
34import freechips.rocketchip.amba.axi4._
35import freechips.rocketchip.jtag.JTAGIO
36import chisel3.experimental.{annotate, ChiselAnnotation}
37import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
38
39abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
40  with BindingScope
41{
42  // val misc = LazyModule(new SoCMisc())
43  lazy val dts = DTS(bindingTree)
44  lazy val json = JSON(bindingTree)
45}
46
47class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
48{
49  val enableCHI = p(EnableCHI)
50
51  val nocMisc = if (enableCHI) Some(LazyModule(new MemMisc())) else None
52  val socMisc = if (!enableCHI) Some(LazyModule(new SoCMisc())) else None
53  val misc: MemMisc = if (enableCHI) nocMisc.get else socMisc.get
54
55  ResourceBinding {
56    val width = ResourceInt(2)
57    val model = "freechips,rocketchip-unknown"
58    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
59    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
60    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
61    Resource(ResourceAnchors.root, "width").bind(width)
62    Resource(ResourceAnchors.soc, "width").bind(width)
63    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
64    def bindManagers(xbar: TLNexusNode) = {
65      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
66        manager.resources.foreach(r => r.bind(manager.toResource))
67      }
68    }
69    bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
70    bindManagers(misc.peripheralXbar.asInstanceOf[TLNexusNode])
71  }
72
73  println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
74
75  val core_with_l2 = tiles.map(coreParams =>
76    LazyModule(new XSTile()(p.alterPartial({
77      case XSCoreParamsKey => coreParams
78    })))
79  )
80
81  val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
82    LazyModule(new HuanCun()(new Config((_, _, _) => {
83      case HCCacheParamsKey => l3param.copy(
84        hartIds = tiles.map(_.HartId),
85        FPGAPlatform = debugOpts.FPGAPlatform
86      )
87      case MaxHartIdBits => p(MaxHartIdBits)
88    })))
89  )
90
91  // recieve all prefetch req from cores
92  val memblock_pf_recv_nodes: Seq[Option[BundleBridgeSink[PrefetchRecv]]] = core_with_l2.map(_.core_l3_pf_port).map{
93    x => x.map(_ => BundleBridgeSink(Some(() => new PrefetchRecv)))
94  }
95
96  val l3_pf_sender_opt = soc.L3CacheParamsOpt.getOrElse(HCCacheParameters()).prefetch match {
97    case Some(pf) => Some(BundleBridgeSource(() => new PrefetchRecv))
98    case None => None
99  }
100
101  for (i <- 0 until NumCores) {
102    core_with_l2(i).clint_int_node := misc.clint.intnode
103    core_with_l2(i).plic_int_node :*= misc.plic.intnode
104    core_with_l2(i).debug_int_node := misc.debugModule.debug.dmOuter.dmOuter.intnode
105    misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
106    if (!enableCHI) {
107      misc.peripheral_ports(i) := core_with_l2(i).tl_uncache
108    } else {
109      // Make diplomacy happy
110      val clientParameters = TLMasterPortParameters.v1(
111        clients = Seq(TLMasterParameters.v1(
112          "uncache"
113        ))
114      )
115      val clientNode = TLClientNode(Seq(clientParameters))
116      misc.peripheral_ports(i) := clientNode
117    }
118    misc.core_to_l3_ports.foreach(port => port(i) :=* core_with_l2(i).memory_port.get)
119    memblock_pf_recv_nodes(i).map(recv => {
120      println(s"Connecting Core_${i}'s L1 pf source to L3!")
121      recv := core_with_l2(i).core_l3_pf_port.get
122    })
123  }
124
125  l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar))
126  l3cacheOpt.map(_.intnode.map(int => {
127    misc.plic.intnode := IntBuffer() := int
128  }))
129
130  val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
131    l3cacheOpt.get.rst_nodes.get
132  } else {
133    core_with_l2.map(_ => BundleBridgeSource(() => Reset()))
134  }
135
136  core_rst_nodes.zip(core_with_l2.map(_.core_reset_sink)).foreach({
137    case (source, sink) =>  sink := source
138  })
139
140  l3cacheOpt match {
141    case Some(l3) =>
142      misc.l3_out :*= l3.node :*= misc.l3_banked_xbar
143      l3.pf_recv_node.map(recv => {
144        println("Connecting L1 prefetcher to L3!")
145        recv := l3_pf_sender_opt.get
146      })
147      l3.tpmeta_recv_node.foreach(recv => {
148        for ((core, i) <- core_with_l2.zipWithIndex) {
149          println(s"Connecting core_$i\'s L2 TPmeta request to L3!")
150          recv := core.core_l3_tpmeta_source_port.get
151        }
152      })
153      l3.tpmeta_send_node.foreach(send => {
154        val broadcast = LazyModule(new ValidIOBroadcast[TPmetaResp]())
155        broadcast.node := send
156        for ((core, i) <- core_with_l2.zipWithIndex) {
157          println(s"Connecting core_$i\'s L2 TPmeta response to L3!")
158          core.core_l3_tpmeta_sink_port.get := broadcast.node
159        }
160      })
161    case None =>
162  }
163
164  class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
165    soc.XSTopPrefix.foreach { prefix =>
166      val mod = this.toNamed
167      annotate(new ChiselAnnotation {
168        def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
169      })
170    }
171
172    FileRegisters.add("dts", dts)
173    FileRegisters.add("graphml", graphML)
174    FileRegisters.add("json", json)
175    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
176
177    val dma = socMisc.map(m => IO(Flipped(m.dma.cloneType)))
178    val peripheral = socMisc.map(m => IO(m.peripheral.cloneType))
179    val memory = IO(misc.memory.cloneType)
180
181    socMisc match {
182      case Some(m) =>
183        m.dma <> dma.get
184        peripheral.get <> m.peripheral
185        dontTouch(dma.get)
186        dontTouch(peripheral.get)
187      case None =>
188    }
189
190    memory <> misc.memory
191
192    val io = IO(new Bundle {
193      val clock = Input(Bool())
194      val reset = Input(AsyncReset())
195      val sram_config = Input(UInt(16.W))
196      val extIntrs = Input(UInt(NrExtIntr.W))
197      val pll0_lock = Input(Bool())
198      val pll0_ctrl = Output(Vec(6, UInt(32.W)))
199      val systemjtag = new Bundle {
200        val jtag = Flipped(new JTAGIO(hasTRSTn = false))
201        val reset = Input(AsyncReset()) // No reset allowed on top
202        val mfr_id = Input(UInt(11.W))
203        val part_number = Input(UInt(16.W))
204        val version = Input(UInt(4.W))
205      }
206      val debug_reset = Output(Bool())
207      val rtc_clock = Input(Bool())
208      val cacheable_check = new TLPMAIO()
209      val riscv_halt = Output(Vec(NumCores, Bool()))
210      val riscv_rst_vec = Input(Vec(NumCores, UInt(38.W)))
211    })
212
213    val reset_sync = withClockAndReset(io.clock.asClock, io.reset) { ResetGen() }
214    val jtag_reset_sync = withClockAndReset(io.systemjtag.jtag.TCK, io.systemjtag.reset) { ResetGen() }
215
216    // override LazyRawModuleImp's clock and reset
217    childClock := io.clock.asClock
218    childReset := reset_sync
219
220    // output
221    io.debug_reset := misc.module.debug_module_io.debugIO.ndreset
222
223    // input
224    dontTouch(io)
225    dontTouch(memory)
226    misc.module.ext_intrs := io.extIntrs
227    misc.module.rtc_clock := io.rtc_clock
228    misc.module.pll0_lock := io.pll0_lock
229    misc.module.cacheable_check <> io.cacheable_check
230
231    io.pll0_ctrl <> misc.module.pll0_ctrl
232
233    for ((core, i) <- core_with_l2.zipWithIndex) {
234      core.module.io.hartId := i.U
235      io.riscv_halt(i) := core.module.io.cpu_halt
236      core.module.io.reset_vector := io.riscv_rst_vec(i)
237    }
238
239    if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
240      // tie off core soft reset
241      for(node <- core_rst_nodes){
242        node.out.head._1 := false.B.asAsyncReset
243      }
244    }
245
246    l3cacheOpt match {
247      case Some(l3) =>
248        l3.pf_recv_node match {
249          case Some(recv) =>
250            l3_pf_sender_opt.get.out.head._1.addr_valid := VecInit(memblock_pf_recv_nodes.map(_.get.in.head._1.addr_valid)).asUInt.orR
251            for (i <- 0 until NumCores) {
252              when(memblock_pf_recv_nodes(i).get.in.head._1.addr_valid) {
253                l3_pf_sender_opt.get.out.head._1.addr := memblock_pf_recv_nodes(i).get.in.head._1.addr
254                l3_pf_sender_opt.get.out.head._1.l2_pf_en := memblock_pf_recv_nodes(i).get.in.head._1.l2_pf_en
255              }
256            }
257          case None =>
258        }
259        l3.module.io.debugTopDown.robHeadPaddr := core_with_l2.map(_.module.io.debugTopDown.robHeadPaddr)
260        core_with_l2.zip(l3.module.io.debugTopDown.addrMatch).foreach { case (tile, l3Match) => tile.module.io.debugTopDown.l3MissMatch := l3Match }
261      case None => core_with_l2.foreach(_.module.io.debugTopDown.l3MissMatch := false.B)
262    }
263
264    core_with_l2.foreach { case tile =>
265      tile.module.io.chi.foreach { case chi_port =>
266        chi_port <> DontCare
267        dontTouch(chi_port)
268      }
269      tile.module.io.nodeID.foreach { case nodeID =>
270        nodeID := DontCare
271        dontTouch(nodeID)
272      }
273    }
274
275    misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
276    misc.module.debug_module_io.clock := io.clock
277    misc.module.debug_module_io.reset := reset_sync
278
279    misc.module.debug_module_io.debugIO.reset := misc.module.reset
280    misc.module.debug_module_io.debugIO.clock := io.clock.asClock
281    // TODO: delay 3 cycles?
282    misc.module.debug_module_io.debugIO.dmactiveAck := misc.module.debug_module_io.debugIO.dmactive
283    // jtag connector
284    misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
285      x.jtag        <> io.systemjtag.jtag
286      x.reset       := jtag_reset_sync
287      x.mfr_id      := io.systemjtag.mfr_id
288      x.part_number := io.systemjtag.part_number
289      x.version     := io.systemjtag.version
290    }
291
292    withClockAndReset(io.clock.asClock, reset_sync) {
293      // Modules are reset one by one
294      // reset ----> SYNC --> {SoCMisc, L3 Cache, Cores}
295      val resetChain = Seq(Seq(misc.module) ++ l3cacheOpt.map(_.module) ++ core_with_l2.map(_.module))
296      ResetGen(resetChain, reset_sync, !debugOpts.ResetGen)
297    }
298
299  }
300
301  lazy val module = new XSTopImp(this)
302}
303
304object TopMain extends App {
305  val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
306
307  // tools: init to close dpi-c when in fpga
308  val envInFPGA = config(DebugOptionsKey).FPGAPlatform
309  val enableDifftest = config(DebugOptionsKey).EnableDifftest
310  val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
311  val enableConstantin = config(DebugOptionsKey).EnableConstantin
312  Constantin.init(enableConstantin && !envInFPGA)
313  ChiselDB.init(enableChiselDB && !envInFPGA)
314
315  val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
316  Generator.execute(firrtlOpts, soc.module, firtoolOpts)
317
318  // generate difftest bundles (w/o DifftestTopIO)
319  if (enableDifftest) {
320    DifftestModule.finish("XiangShan", false)
321  }
322
323  FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.")
324}
325