xref: /XiangShan/src/main/scala/top/Top.scala (revision 0466583513e4c1ddbbb566b866b8963635acb20f) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import utility._
24import system._
25import device._
26import chisel3.stage.ChiselGeneratorAnnotation
27import chipsalliance.rocketchip.config._
28import freechips.rocketchip.diplomacy._
29import freechips.rocketchip.tilelink._
30import freechips.rocketchip.jtag.JTAGIO
31import freechips.rocketchip.util.{HasRocketChipStageUtils, UIntToOH1}
32import huancun.{HCCacheParamsKey, HuanCun}
33
34abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
35  with BindingScope
36{
37  val misc = LazyModule(new SoCMisc())
38  lazy val dts = DTS(bindingTree)
39  lazy val json = JSON(bindingTree)
40}
41
42class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
43{
44  ResourceBinding {
45    val width = ResourceInt(2)
46    val model = "freechips,rocketchip-unknown"
47    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
48    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
49    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
50    Resource(ResourceAnchors.root, "width").bind(width)
51    Resource(ResourceAnchors.soc, "width").bind(width)
52    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
53    def bindManagers(xbar: TLNexusNode) = {
54      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
55        manager.resources.foreach(r => r.bind(manager.toResource))
56      }
57    }
58    bindManagers(misc.l3_xbar.asInstanceOf[TLNexusNode])
59    bindManagers(misc.peripheralXbar.asInstanceOf[TLNexusNode])
60  }
61
62  println(s"FPGASoC cores: $NumCores banks: $L3NBanks block size: $L3BlockSize bus size: $L3OuterBusWidth")
63
64  val core_with_l2 = tiles.map(coreParams =>
65    LazyModule(new XSTile()(p.alterPartial({
66      case XSCoreParamsKey => coreParams
67    })))
68  )
69
70  val l3cacheOpt = soc.L3CacheParamsOpt.map(l3param =>
71    LazyModule(new HuanCun()(new Config((_, _, _) => {
72      case HCCacheParamsKey => l3param.copy(hartIds = tiles.map(_.HartId))
73    })))
74  )
75
76  for (i <- 0 until NumCores) {
77    core_with_l2(i).clint_int_sink := misc.clint.intnode
78    core_with_l2(i).plic_int_sink :*= misc.plic.intnode
79    core_with_l2(i).debug_int_sink := misc.debugModule.debug.dmOuter.dmOuter.intnode
80    misc.plic.intnode := IntBuffer() := core_with_l2(i).beu_int_source
81    misc.peripheral_ports(i) := core_with_l2(i).uncache
82    misc.core_to_l3_ports(i) :=* core_with_l2(i).memory_port
83  }
84
85  l3cacheOpt.map(_.ctlnode.map(_ := misc.peripheralXbar))
86  l3cacheOpt.map(_.intnode.map(int => {
87    misc.plic.intnode := IntBuffer() := int
88  }))
89
90  val core_rst_nodes = if(l3cacheOpt.nonEmpty && l3cacheOpt.get.rst_nodes.nonEmpty){
91    l3cacheOpt.get.rst_nodes.get
92  } else {
93    core_with_l2.map(_ => BundleBridgeSource(() => Reset()))
94  }
95
96  core_rst_nodes.zip(core_with_l2.map(_.core_reset_sink)).foreach({
97    case (source, sink) =>  sink := source
98  })
99
100  l3cacheOpt match {
101    case Some(l3) =>
102      misc.l3_out :*= l3.node :*= misc.l3_banked_xbar
103    case None =>
104      val dummyMatch = WireDefault(false.B)
105      tiles.map(_.HartId).foreach(hartId => ExcitingUtils.addSource(dummyMatch, s"L3MissMatch_${hartId}", ExcitingUtils.Perf, true))
106  }
107
108  lazy val module = new LazyRawModuleImp(this) {
109    FileRegisters.add("dts", dts)
110    FileRegisters.add("graphml", graphML)
111    FileRegisters.add("json", json)
112    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
113
114    val dma = IO(Flipped(misc.dma.cloneType))
115    val peripheral = IO(misc.peripheral.cloneType)
116    val memory = IO(misc.memory.cloneType)
117
118    misc.dma <> dma
119    peripheral <> misc.peripheral
120    memory <> misc.memory
121
122    val io = IO(new Bundle {
123      val clock = Input(Bool())
124      val reset = Input(AsyncReset())
125      val sram_config = Input(UInt(16.W))
126      val extIntrs = Input(UInt(NrExtIntr.W))
127      val pll0_lock = Input(Bool())
128      val pll0_ctrl = Output(Vec(6, UInt(32.W)))
129      val systemjtag = new Bundle {
130        val jtag = Flipped(new JTAGIO(hasTRSTn = false))
131        val reset = Input(AsyncReset()) // No reset allowed on top
132        val mfr_id = Input(UInt(11.W))
133        val part_number = Input(UInt(16.W))
134        val version = Input(UInt(4.W))
135      }
136      val debug_reset = Output(Bool())
137      val rtc_clock = Input(Bool())
138      val cacheable_check = new TLPMAIO()
139      val riscv_halt = Output(Vec(NumCores, Bool()))
140      val riscv_rst_vec = Input(Vec(NumCores, UInt(38.W)))
141    })
142
143    val reset_sync = withClockAndReset(io.clock.asClock, io.reset) { ResetGen() }
144    val jtag_reset_sync = withClockAndReset(io.systemjtag.jtag.TCK, io.systemjtag.reset) { ResetGen() }
145
146    // override LazyRawModuleImp's clock and reset
147    childClock := io.clock.asClock
148    childReset := reset_sync
149
150    // output
151    io.debug_reset := misc.module.debug_module_io.debugIO.ndreset
152
153    // input
154    dontTouch(dma)
155    dontTouch(io)
156    dontTouch(peripheral)
157    dontTouch(memory)
158    misc.module.ext_intrs := io.extIntrs
159    misc.module.rtc_clock := io.rtc_clock
160    misc.module.pll0_lock := io.pll0_lock
161    misc.module.cacheable_check <> io.cacheable_check
162
163    io.pll0_ctrl <> misc.module.pll0_ctrl
164
165    for ((core, i) <- core_with_l2.zipWithIndex) {
166      core.module.io.hartId := i.U
167      io.riscv_halt(i) := core.module.io.cpu_halt
168      core.module.io.reset_vector := io.riscv_rst_vec(i)
169    }
170
171    if(l3cacheOpt.isEmpty || l3cacheOpt.get.rst_nodes.isEmpty){
172      // tie off core soft reset
173      for(node <- core_rst_nodes){
174        node.out.head._1 := false.B.asAsyncReset()
175      }
176    }
177
178    misc.module.debug_module_io.resetCtrl.hartIsInReset := core_with_l2.map(_.module.reset.asBool)
179    misc.module.debug_module_io.clock := io.clock
180    misc.module.debug_module_io.reset := reset_sync
181
182    misc.module.debug_module_io.debugIO.reset := misc.module.reset
183    misc.module.debug_module_io.debugIO.clock := io.clock.asClock
184    // TODO: delay 3 cycles?
185    misc.module.debug_module_io.debugIO.dmactiveAck := misc.module.debug_module_io.debugIO.dmactive
186    // jtag connector
187    misc.module.debug_module_io.debugIO.systemjtag.foreach { x =>
188      x.jtag        <> io.systemjtag.jtag
189      x.reset       := jtag_reset_sync
190      x.mfr_id      := io.systemjtag.mfr_id
191      x.part_number := io.systemjtag.part_number
192      x.version     := io.systemjtag.version
193    }
194
195    withClockAndReset(io.clock.asClock, reset_sync) {
196      // Modules are reset one by one
197      // reset ----> SYNC --> {SoCMisc, L3 Cache, Cores}
198      val resetChain = Seq(Seq(misc.module) ++ l3cacheOpt.map(_.module) ++ core_with_l2.map(_.module))
199      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
200    }
201
202  }
203}
204
205object TopMain extends App with HasRocketChipStageUtils {
206  override def main(args: Array[String]): Unit = {
207    val (config, firrtlOpts, firrtlComplier, firtoolOpts) = ArgParser.parse(args)
208
209    // tools: init to close dpi-c when in fpga
210    val envInFPGA = config(DebugOptionsKey).FPGAPlatform
211    val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
212    val enableConstantin = config(DebugOptionsKey).EnableConstantin
213    Constantin.init(enableConstantin && !envInFPGA)
214    ChiselDB.init(enableChiselDB && !envInFPGA)
215
216    val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
217    Generator.execute(firrtlOpts, soc.module, firrtlComplier, firtoolOpts)
218    FileRegisters.write(fileDir = "./build", filePrefix = "XSTop.")
219  }
220}
221