1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3.RawModule 20import chisel3.stage.{ChiselCli, ChiselGeneratorAnnotation} 21import firrtl.options.Shell 22import firrtl.stage.{FirrtlCli, RunFirrtlTransformAnnotation} 23import freechips.rocketchip.transforms.naming.RenameDesiredNames 24import xstransforms._ 25 26trait XiangShanCli { this: Shell => 27 parser.note("XiangShan Options") 28 DisablePrintfAnnotation.addOptions(parser) 29 EnablePrintfAnnotation.addOptions(parser) 30 DisableAllPrintAnnotation.addOptions(parser) 31 RemoveAssertAnnotation.addOptions(parser) 32} 33 34class XiangShanStage extends chisel3.stage.ChiselStage { 35 override val shell: Shell = new Shell("xiangshan") 36 with XiangShanCli 37 with ChiselCli 38 with FirrtlCli 39} 40 41abstract class FirrtlCompiler 42case object SFC extends FirrtlCompiler 43case object MFC extends FirrtlCompiler 44 45object Generator { 46 47 def execute(args: Array[String], mod: => RawModule, fc: FirrtlCompiler) = { 48 fc match { 49 case MFC => 50 val sfcXsTransforms = Seq( 51 DisablePrintfAnnotation, 52 EnablePrintfAnnotation, 53 DisableAllPrintAnnotation, 54 RemoveAssertAnnotation 55 ) 56 val sfcOptions = sfcXsTransforms.flatMap(_.options.map(_.longOption)) ++ 57 sfcXsTransforms.flatMap(_.options.flatMap(_.shortOption)) 58 val mfcArgs = args.filter(s => { 59 val option_s = if(s.startsWith("--")){ 60 s.replace("--", "") 61 } else if(s.startsWith("-")){ 62 s.replace("-", "") 63 } else s 64 val cond = sfcOptions.contains(option_s) 65 if(cond){ 66 println(s"[Warnning] SFC Transform Option ${s} will be removed in MFC!") 67 } 68 !cond 69 }) 70 (new circt.stage.ChiselStage).execute(mfcArgs, Seq( 71 ChiselGeneratorAnnotation(mod _), 72 circt.stage.CIRCTTargetAnnotation(circt.stage.CIRCTTarget.Verilog), 73 circt.stage.CIRCTHandover(circt.stage.CIRCTHandover.CHIRRTL) 74 )) 75 case SFC => 76 (new XiangShanStage).execute(args, Seq( 77 ChiselGeneratorAnnotation(mod _), 78 RunFirrtlTransformAnnotation(new PrintControl), 79 RunFirrtlTransformAnnotation(new PrintModuleName), 80 RunFirrtlTransformAnnotation(new RenameDesiredNames) 81 )) 82 case _ => 83 assert(false, s"Unknown firrtl compiler: ${fc.getClass.getName}!") 84 } 85 } 86 87} 88