xref: /XiangShan/src/main/scala/top/Generator.scala (revision 6ce1096467c77f9a13c9ea0e57b870cd1fb67270)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import circt.stage._
20import chisel3.stage.ChiselGeneratorAnnotation
21import xiangshan.types._
22
23object Generator {
24  val chiselVersion = chisel3.BuildInfo.version
25
26  def execute(args: Array[String], mod: => chisel3.RawModule, firtoolOpts: Array[String]) = {
27    val annotations = chiselVersion match {
28      case "3.6.0" => Seq(
29        RunFirrtlTransformAnnotation(new PrintControl),
30        RunFirrtlTransformAnnotation(new PrintModuleName)
31      )
32      case _ => Seq(
33        CIRCTTargetAnnotation(CIRCTTarget.Verilog)
34      ) ++ firtoolOpts.map(opt => FirtoolOption(opt))
35    }
36
37    (new XiangShanStage).execute(args, ChiselGeneratorAnnotation(mod _) +: annotations)
38  }
39}
40