1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import chipsalliance.rocketchip.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.MaxHartIdBits 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.exu.ExuParameters 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36import coupledL2._ 37 38class BaseConfig(n: Int) extends Config((site, here, up) => { 39 case XLen => 64 40 case DebugOptionsKey => DebugOptions() 41 case SoCParamsKey => SoCParameters() 42 case PMParameKey => PMParameters() 43 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 44 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 45 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 46 case JtagDTMKey => JtagDTMKey 47 case MaxHartIdBits => 2 48 case EnableJtag => true.B 49}) 50 51// Synthesizable minimal XiangShan 52// * It is still an out-of-order, super-scalaer arch 53// * L1 cache included 54// * L2 cache NOT included 55// * L3 cache included 56class MinimalConfig(n: Int = 1) extends Config( 57 new BaseConfig(n).alter((site, here, up) => { 58 case XSTileKey => up(XSTileKey).map( 59 _.copy( 60 DecodeWidth = 2, 61 RenameWidth = 2, 62 CommitWidth = 2, 63 FetchWidth = 4, 64 IssQueSize = 8, 65 NRPhyRegs = 64, 66 VirtualLoadQueueSize = 16, 67 LoadQueueRARSize = 16, 68 LoadQueueRAWSize = 12, 69 LoadQueueReplaySize = 8, 70 LoadUncacheBufferSize = 8, 71 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 72 RollbackGroupSize = 8, 73 StoreQueueSize = 12, 74 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 75 StoreQueueForwardWithMask = true, 76 RobSize = 32, 77 FtqSize = 8, 78 IBufSize = 16, 79 StoreBufferSize = 4, 80 StoreBufferThreshold = 3, 81 dpParams = DispatchParameters( 82 IntDqSize = 12, 83 FpDqSize = 12, 84 LsDqSize = 12, 85 IntDqDeqWidth = 4, 86 FpDqDeqWidth = 4, 87 LsDqDeqWidth = 4 88 ), 89 exuParameters = ExuParameters( 90 JmpCnt = 1, 91 AluCnt = 2, 92 MulCnt = 0, 93 MduCnt = 1, 94 FmacCnt = 1, 95 FmiscCnt = 1, 96 FmiscDivSqrtCnt = 0, 97 LduCnt = 2, 98 StuCnt = 2 99 ), 100 icacheParameters = ICacheParameters( 101 nSets = 64, // 16KB ICache 102 tagECC = Some("parity"), 103 dataECC = Some("parity"), 104 replacer = Some("setplru"), 105 nMissEntries = 2, 106 nReleaseEntries = 1, 107 nProbeEntries = 2, 108 nPrefetchEntries = 2, 109 nPrefBufferEntries = 32, 110 hasPrefetch = true 111 ), 112 dcacheParametersOpt = Some(DCacheParameters( 113 nSets = 64, // 32KB DCache 114 nWays = 8, 115 tagECC = Some("secded"), 116 dataECC = Some("secded"), 117 replacer = Some("setplru"), 118 nMissEntries = 4, 119 nProbeEntries = 4, 120 nReleaseEntries = 8, 121 )), 122 EnableBPD = false, // disable TAGE 123 EnableLoop = false, 124 itlbParameters = TLBParameters( 125 name = "itlb", 126 fetchi = true, 127 useDmode = false, 128 normalReplacer = Some("plru"), 129 superReplacer = Some("plru"), 130 normalNWays = 4, 131 normalNSets = 1, 132 superNWays = 2 133 ), 134 ldtlbParameters = TLBParameters( 135 name = "ldtlb", 136 normalNSets = 16, // when da or sa 137 normalNWays = 1, // when fa or sa 138 normalAssociative = "sa", 139 normalReplacer = Some("setplru"), 140 superNWays = 4, 141 normalAsVictim = true, 142 partialStaticPMP = true, 143 outsideRecvFlush = true, 144 outReplace = false 145 ), 146 sttlbParameters = TLBParameters( 147 name = "sttlb", 148 normalNSets = 16, // when da or sa 149 normalNWays = 1, // when fa or sa 150 normalAssociative = "sa", 151 normalReplacer = Some("setplru"), 152 normalAsVictim = true, 153 superNWays = 4, 154 partialStaticPMP = true, 155 outsideRecvFlush = true, 156 outReplace = false 157 ), 158 pftlbParameters = TLBParameters( 159 name = "pftlb", 160 normalNSets = 16, // when da or sa 161 normalNWays = 1, // when fa or sa 162 normalAssociative = "sa", 163 normalReplacer = Some("setplru"), 164 normalAsVictim = true, 165 superNWays = 4, 166 partialStaticPMP = true, 167 outsideRecvFlush = true, 168 outReplace = false 169 ), 170 btlbParameters = TLBParameters( 171 name = "btlb", 172 normalNSets = 1, 173 normalNWays = 8, 174 superNWays = 2 175 ), 176 l2tlbParameters = L2TLBParameters( 177 l1Size = 4, 178 l2nSets = 4, 179 l2nWays = 4, 180 l3nSets = 4, 181 l3nWays = 8, 182 spSize = 2, 183 ), 184 L2CacheParamsOpt = Some(L2Param( 185 name = "L2", 186 ways = 8, 187 sets = 128, 188 echoField = Seq(huancun.DirtyField()), 189 prefetch = None 190 )), 191 L2NBanks = 2, 192 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 193 ) 194 ) 195 case SoCParamsKey => 196 val tiles = site(XSTileKey) 197 up(SoCParamsKey).copy( 198 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 199 sets = 1024, 200 inclusive = false, 201 clientCaches = tiles.map{ core => 202 val clientDirBytes = tiles.map{ t => 203 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 204 }.sum 205 val l2params = core.L2CacheParamsOpt.get.toCacheParams 206 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 207 }, 208 simulation = !site(DebugOptionsKey).FPGAPlatform 209 )), 210 L3NBanks = 1 211 ) 212 }) 213) 214 215// Non-synthesizable MinimalConfig, for fast simulation only 216class MinimalSimConfig(n: Int = 1) extends Config( 217 new MinimalConfig(n).alter((site, here, up) => { 218 case XSTileKey => up(XSTileKey).map(_.copy( 219 dcacheParametersOpt = None, 220 softPTW = true 221 )) 222 case SoCParamsKey => up(SoCParamsKey).copy( 223 L3CacheParamsOpt = None 224 ) 225 }) 226) 227 228class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 229 case XSTileKey => 230 val sets = n * 1024 / ways / 64 231 up(XSTileKey).map(_.copy( 232 dcacheParametersOpt = Some(DCacheParameters( 233 nSets = sets, 234 nWays = ways, 235 tagECC = Some("secded"), 236 dataECC = Some("secded"), 237 replacer = Some("setplru"), 238 nMissEntries = 16, 239 nProbeEntries = 8, 240 nReleaseEntries = 18 241 )) 242 )) 243}) 244 245class WithNKBL2 246( 247 n: Int, 248 ways: Int = 8, 249 inclusive: Boolean = true, 250 banks: Int = 1 251) extends Config((site, here, up) => { 252 case XSTileKey => 253 val upParams = up(XSTileKey) 254 val l2sets = n * 1024 / banks / ways / 64 255 upParams.map(p => p.copy( 256 L2CacheParamsOpt = Some(L2Param( 257 name = "L2", 258 ways = ways, 259 sets = l2sets, 260 clientCaches = Seq(L1Param( 261 "dcache", 262 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 263 ways = p.dcacheParametersOpt.get.nWays + 2, 264 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 265 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)) 266 )), 267 reqField = Seq(utility.ReqSourceField()), 268 echoField = Seq(huancun.DirtyField()), 269 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 270 )), 271 L2NBanks = banks 272 )) 273}) 274 275class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 276 case SoCParamsKey => 277 val sets = n * 1024 / banks / ways / 64 278 val tiles = site(XSTileKey) 279 val clientDirBytes = tiles.map{ t => 280 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 281 }.sum 282 up(SoCParamsKey).copy( 283 L3NBanks = banks, 284 L3CacheParamsOpt = Some(HCCacheParameters( 285 name = "L3", 286 level = 3, 287 ways = ways, 288 sets = sets, 289 inclusive = inclusive, 290 clientCaches = tiles.map{ core => 291 val l2params = core.L2CacheParamsOpt.get.toCacheParams 292 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 293 }, 294 enablePerf = true, 295 ctrl = Some(CacheCtrl( 296 address = 0x39000000, 297 numCores = tiles.size 298 )), 299 reqField = Seq(utility.ReqSourceField()), 300 sramClkDivBy2 = true, 301 sramDepthDiv = 4, 302 tagECC = Some("secded"), 303 dataECC = Some("secded"), 304 simulation = !site(DebugOptionsKey).FPGAPlatform 305 )) 306 ) 307}) 308 309class WithL3DebugConfig extends Config( 310 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 311) 312 313class MinimalL3DebugConfig(n: Int = 1) extends Config( 314 new WithL3DebugConfig ++ new MinimalConfig(n) 315) 316 317class DefaultL3DebugConfig(n: Int = 1) extends Config( 318 new WithL3DebugConfig ++ new BaseConfig(n) 319) 320 321class MinimalAliasDebugConfig(n: Int = 1) extends Config( 322 new WithNKBL3(512, inclusive = false) ++ 323 new WithNKBL2(256, inclusive = false) ++ 324 new WithNKBL1D(128) ++ 325 new MinimalConfig(n) 326) 327 328class MediumConfig(n: Int = 1) extends Config( 329 new WithNKBL3(4096, inclusive = false, banks = 4) 330 ++ new WithNKBL2(512, inclusive = false) 331 ++ new WithNKBL1D(128) 332 ++ new BaseConfig(n) 333) 334 335class DefaultConfig(n: Int = 1) extends Config( 336 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 337 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4) 338 ++ new WithNKBL1D(128) 339 ++ new BaseConfig(n) 340) 341