1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import xiangshan.frontend.icache.ICacheParameters 43 44class BaseConfig(n: Int) extends Config((site, here, up) => { 45 case XLen => 64 46 case DebugOptionsKey => DebugOptions() 47 case SoCParamsKey => SoCParameters() 48 case PMParameKey => PMParameters() 49 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 50 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 51 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 52 case JtagDTMKey => JtagDTMKey 53 case MaxHartIdBits => log2Up(n) 54 case EnableJtag => true.B 55}) 56 57// Synthesizable minimal XiangShan 58// * It is still an out-of-order, super-scalaer arch 59// * L1 cache included 60// * L2 cache NOT included 61// * L3 cache included 62class MinimalConfig(n: Int = 1) extends Config( 63 new BaseConfig(n).alter((site, here, up) => { 64 case XSTileKey => up(XSTileKey).map( 65 p => p.copy( 66 DecodeWidth = 6, 67 RenameWidth = 6, 68 RobCommitWidth = 8, 69 FetchWidth = 4, 70 VirtualLoadQueueSize = 24, 71 LoadQueueRARSize = 16, 72 LoadQueueRAWSize = 12, 73 LoadQueueReplaySize = 24, 74 LoadUncacheBufferSize = 8, 75 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 76 RollbackGroupSize = 8, 77 StoreQueueSize = 20, 78 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 79 StoreQueueForwardWithMask = true, 80 RobSize = 48, 81 RabSize = 96, 82 FtqSize = 8, 83 IBufSize = 24, 84 IBufNBank = 6, 85 StoreBufferSize = 4, 86 StoreBufferThreshold = 3, 87 IssueQueueSize = 8, 88 IssueQueueCompEntrySize = 4, 89 dpParams = DispatchParameters( 90 IntDqSize = 12, 91 FpDqSize = 12, 92 LsDqSize = 12, 93 IntDqDeqWidth = 8, 94 FpDqDeqWidth = 4, 95 LsDqDeqWidth = 6 96 ), 97 intPreg = IntPregParams( 98 numEntries = 64, 99 numRead = None, 100 numWrite = None, 101 ), 102 vfPreg = VfPregParams( 103 numEntries = 160, 104 numRead = Some(14), 105 numWrite = None, 106 ), 107 icacheParameters = ICacheParameters( 108 nSets = 64, // 16KB ICache 109 tagECC = Some("parity"), 110 dataECC = Some("parity"), 111 replacer = Some("setplru"), 112 nMissEntries = 2, 113 nReleaseEntries = 1, 114 nProbeEntries = 2, 115 // fdip 116 enableICachePrefetch = true, 117 prefetchToL1 = false, 118 ), 119 dcacheParametersOpt = Some(DCacheParameters( 120 nSets = 64, // 32KB DCache 121 nWays = 8, 122 tagECC = Some("secded"), 123 dataECC = Some("secded"), 124 replacer = Some("setplru"), 125 nMissEntries = 4, 126 nProbeEntries = 4, 127 nReleaseEntries = 8, 128 nMaxPrefetchEntry = 2, 129 )), 130 EnableBPD = false, // disable TAGE 131 EnableLoop = false, 132 itlbParameters = TLBParameters( 133 name = "itlb", 134 fetchi = true, 135 useDmode = false, 136 NWays = 4, 137 ), 138 ldtlbParameters = TLBParameters( 139 name = "ldtlb", 140 NWays = 4, 141 partialStaticPMP = true, 142 outsideRecvFlush = true, 143 outReplace = false 144 ), 145 sttlbParameters = TLBParameters( 146 name = "sttlb", 147 NWays = 4, 148 partialStaticPMP = true, 149 outsideRecvFlush = true, 150 outReplace = false 151 ), 152 hytlbParameters = TLBParameters( 153 name = "hytlb", 154 NWays = 4, 155 partialStaticPMP = true, 156 outsideRecvFlush = true, 157 outReplace = false 158 ), 159 pftlbParameters = TLBParameters( 160 name = "pftlb", 161 NWays = 4, 162 partialStaticPMP = true, 163 outsideRecvFlush = true, 164 outReplace = false 165 ), 166 btlbParameters = TLBParameters( 167 name = "btlb", 168 NWays = 4, 169 ), 170 l2tlbParameters = L2TLBParameters( 171 l1Size = 4, 172 l2nSets = 4, 173 l2nWays = 4, 174 l3nSets = 4, 175 l3nWays = 8, 176 spSize = 2, 177 ), 178 L2CacheParamsOpt = Some(L2Param( 179 name = "L2", 180 ways = 8, 181 sets = 128, 182 echoField = Seq(huancun.DirtyField()), 183 prefetch = None, 184 clientCaches = Seq(L1Param( 185 "dcache", 186 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 187 )), 188 ) 189 ), 190 L2NBanks = 2, 191 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 192 ) 193 ) 194 case SoCParamsKey => 195 val tiles = site(XSTileKey) 196 up(SoCParamsKey).copy( 197 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 198 sets = 1024, 199 inclusive = false, 200 clientCaches = tiles.map{ core => 201 val clientDirBytes = tiles.map{ t => 202 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 203 }.sum 204 val l2params = core.L2CacheParamsOpt.get.toCacheParams 205 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 206 }, 207 simulation = !site(DebugOptionsKey).FPGAPlatform, 208 prefetch = None 209 )), 210 L3NBanks = 1 211 ) 212 }) 213) 214 215// Non-synthesizable MinimalConfig, for fast simulation only 216class MinimalSimConfig(n: Int = 1) extends Config( 217 new MinimalConfig(n).alter((site, here, up) => { 218 case XSTileKey => up(XSTileKey).map(_.copy( 219 dcacheParametersOpt = None, 220 softPTW = true 221 )) 222 case SoCParamsKey => up(SoCParamsKey).copy( 223 L3CacheParamsOpt = None 224 ) 225 }) 226) 227 228class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 229 case XSTileKey => 230 val sets = n * 1024 / ways / 64 231 up(XSTileKey).map(_.copy( 232 dcacheParametersOpt = Some(DCacheParameters( 233 nSets = sets, 234 nWays = ways, 235 tagECC = Some("secded"), 236 dataECC = Some("secded"), 237 replacer = Some("setplru"), 238 nMissEntries = 16, 239 nProbeEntries = 8, 240 nReleaseEntries = 18, 241 nMaxPrefetchEntry = 6, 242 )) 243 )) 244}) 245 246class WithNKBL2 247( 248 n: Int, 249 ways: Int = 8, 250 inclusive: Boolean = true, 251 banks: Int = 1 252) extends Config((site, here, up) => { 253 case XSTileKey => 254 require(inclusive, "L2 must be inclusive") 255 val upParams = up(XSTileKey) 256 val l2sets = n * 1024 / banks / ways / 64 257 upParams.map(p => p.copy( 258 L2CacheParamsOpt = Some(L2Param( 259 name = "L2", 260 ways = ways, 261 sets = l2sets, 262 clientCaches = Seq(L1Param( 263 "dcache", 264 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 265 ways = p.dcacheParametersOpt.get.nWays + 2, 266 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 267 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)), 268 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 269 )), 270 reqField = Seq(utility.ReqSourceField()), 271 echoField = Seq(huancun.DirtyField()), 272 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()), 273 enablePerf = !site(DebugOptionsKey).FPGAPlatform, 274 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 275 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 276 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 277 )), 278 L2NBanks = banks 279 )) 280}) 281 282class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 283 case SoCParamsKey => 284 val sets = n * 1024 / banks / ways / 64 285 val tiles = site(XSTileKey) 286 val clientDirBytes = tiles.map{ t => 287 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 288 }.sum 289 up(SoCParamsKey).copy( 290 L3NBanks = banks, 291 L3CacheParamsOpt = Some(HCCacheParameters( 292 name = "L3", 293 level = 3, 294 ways = ways, 295 sets = sets, 296 inclusive = inclusive, 297 clientCaches = tiles.map{ core => 298 val l2params = core.L2CacheParamsOpt.get.toCacheParams 299 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 300 }, 301 enablePerf = true, 302 ctrl = Some(CacheCtrl( 303 address = 0x39000000, 304 numCores = tiles.size 305 )), 306 reqField = Seq(utility.ReqSourceField()), 307 sramClkDivBy2 = true, 308 sramDepthDiv = 4, 309 tagECC = Some("secded"), 310 dataECC = Some("secded"), 311 simulation = !site(DebugOptionsKey).FPGAPlatform, 312 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 313 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 314 )) 315 ) 316}) 317 318class WithL3DebugConfig extends Config( 319 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 320) 321 322class MinimalL3DebugConfig(n: Int = 1) extends Config( 323 new WithL3DebugConfig ++ new MinimalConfig(n) 324) 325 326class DefaultL3DebugConfig(n: Int = 1) extends Config( 327 new WithL3DebugConfig ++ new BaseConfig(n) 328) 329 330class WithFuzzer extends Config((site, here, up) => { 331 case DebugOptionsKey => up(DebugOptionsKey).copy( 332 EnablePerfDebug = false, 333 ) 334 case SoCParamsKey => up(SoCParamsKey).copy( 335 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 336 enablePerf = false, 337 )), 338 ) 339 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 340 p.copy( 341 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 342 enablePerf = false, 343 )), 344 ) 345 } 346}) 347 348class MinimalAliasDebugConfig(n: Int = 1) extends Config( 349 new WithNKBL3(512, inclusive = false) ++ 350 new WithNKBL2(256, inclusive = true) ++ 351 new WithNKBL1D(128) ++ 352 new MinimalConfig(n) 353) 354 355class MediumConfig(n: Int = 1) extends Config( 356 new WithNKBL3(4096, inclusive = false, banks = 4) 357 ++ new WithNKBL2(512, inclusive = true) 358 ++ new WithNKBL1D(128) 359 ++ new BaseConfig(n) 360) 361 362class FuzzConfig(dummy: Int = 0) extends Config( 363 new WithFuzzer 364 ++ new DefaultConfig(1) 365) 366 367class DefaultConfig(n: Int = 1) extends Config( 368 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 369 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 370 ++ new WithNKBL1D(64, ways = 4) 371 ++ new BaseConfig(n) 372) 373