1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import chipsalliance.rocketchip.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.MaxHartIdBits 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.exu.ExuParameters 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36 37class BaseConfig(n: Int) extends Config((site, here, up) => { 38 case XLen => 64 39 case DebugOptionsKey => DebugOptions() 40 case SoCParamsKey => SoCParameters() 41 case PMParameKey => PMParameters() 42 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 43 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 44 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 45 case JtagDTMKey => JtagDTMKey 46 case MaxHartIdBits => 2 47 case EnableJtag => true.B 48}) 49 50// Synthesizable minimal XiangShan 51// * It is still an out-of-order, super-scalaer arch 52// * L1 cache included 53// * L2 cache NOT included 54// * L3 cache included 55class MinimalConfig(n: Int = 1) extends Config( 56 new BaseConfig(n).alter((site, here, up) => { 57 case XSTileKey => up(XSTileKey).map( 58 _.copy( 59 DecodeWidth = 2, 60 RenameWidth = 2, 61 CommitWidth = 2, 62 FetchWidth = 4, 63 IssQueSize = 8, 64 NRPhyRegs = 96, 65 IntPhyRegs = 96, 66 VfPhyRegs = 96, 67 LoadQueueSize = 16, 68 LoadQueueNWriteBanks = 4, 69 StoreQueueSize = 12, 70 StoreQueueNWriteBanks = 4, 71 RobSize = 32, 72 FtqSize = 8, 73 IBufSize = 16, 74 StoreBufferSize = 4, 75 StoreBufferThreshold = 3, 76 dpParams = DispatchParameters( 77 IntDqSize = 12, 78 FpDqSize = 12, 79 LsDqSize = 12, 80 IntDqDeqWidth = 4, 81 FpDqDeqWidth = 4, 82 LsDqDeqWidth = 4 83 ), 84 exuParameters = ExuParameters( 85 JmpCnt = 1, 86 AluCnt = 2, 87 MulCnt = 0, 88 MduCnt = 1, 89 FmacCnt = 1, 90 FmiscCnt = 1, 91 FmiscDivSqrtCnt = 0, 92 LduCnt = 2, 93 StuCnt = 2 94 ), 95 icacheParameters = ICacheParameters( 96 nSets = 64, // 16KB ICache 97 tagECC = Some("parity"), 98 dataECC = Some("parity"), 99 replacer = Some("setplru"), 100 nMissEntries = 2, 101 nReleaseEntries = 1, 102 nProbeEntries = 2, 103 nPrefetchEntries = 2, 104 hasPrefetch = false 105 ), 106 dcacheParametersOpt = Some(DCacheParameters( 107 nSets = 64, // 32KB DCache 108 nWays = 8, 109 tagECC = Some("secded"), 110 dataECC = Some("secded"), 111 replacer = Some("setplru"), 112 nMissEntries = 4, 113 nProbeEntries = 4, 114 nReleaseEntries = 8, 115 )), 116 EnableBPD = false, // disable TAGE 117 EnableLoop = false, 118 itlbParameters = TLBParameters( 119 name = "itlb", 120 fetchi = true, 121 useDmode = false, 122 normalReplacer = Some("plru"), 123 superReplacer = Some("plru"), 124 normalNWays = 4, 125 normalNSets = 1, 126 superNWays = 2 127 ), 128 ldtlbParameters = TLBParameters( 129 name = "ldtlb", 130 normalNSets = 16, // when da or sa 131 normalNWays = 1, // when fa or sa 132 normalAssociative = "sa", 133 normalReplacer = Some("setplru"), 134 superNWays = 4, 135 normalAsVictim = true, 136 partialStaticPMP = true, 137 outsideRecvFlush = true, 138 outReplace = false 139 ), 140 sttlbParameters = TLBParameters( 141 name = "sttlb", 142 normalNSets = 16, // when da or sa 143 normalNWays = 1, // when fa or sa 144 normalAssociative = "sa", 145 normalReplacer = Some("setplru"), 146 normalAsVictim = true, 147 superNWays = 4, 148 partialStaticPMP = true, 149 outsideRecvFlush = true, 150 outReplace = false 151 ), 152 pftlbParameters = TLBParameters( 153 name = "pftlb", 154 normalNSets = 16, // when da or sa 155 normalNWays = 1, // when fa or sa 156 normalAssociative = "sa", 157 normalReplacer = Some("setplru"), 158 normalAsVictim = true, 159 superNWays = 4, 160 partialStaticPMP = true, 161 outsideRecvFlush = true, 162 outReplace = false 163 ), 164 btlbParameters = TLBParameters( 165 name = "btlb", 166 normalNSets = 1, 167 normalNWays = 8, 168 superNWays = 2 169 ), 170 l2tlbParameters = L2TLBParameters( 171 l1Size = 4, 172 l2nSets = 4, 173 l2nWays = 4, 174 l3nSets = 4, 175 l3nWays = 8, 176 spSize = 2, 177 ), 178 L2CacheParamsOpt = None, // remove L2 Cache 179 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 180 ) 181 ) 182 case SoCParamsKey => 183 val tiles = site(XSTileKey) 184 up(SoCParamsKey).copy( 185 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 186 sets = 1024, 187 inclusive = false, 188 clientCaches = tiles.map{ p => 189 CacheParameters( 190 "dcache", 191 sets = 2 * p.dcacheParametersOpt.get.nSets, 192 ways = p.dcacheParametersOpt.get.nWays + 2, 193 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets), 194 aliasBitsOpt = None 195 ) 196 }, 197 simulation = !site(DebugOptionsKey).FPGAPlatform 198 )), 199 L3NBanks = 1 200 ) 201 }) 202) 203 204// Non-synthesizable MinimalConfig, for fast simulation only 205class MinimalSimConfig(n: Int = 1) extends Config( 206 new MinimalConfig(n).alter((site, here, up) => { 207 case XSTileKey => up(XSTileKey).map(_.copy( 208 dcacheParametersOpt = None, 209 softPTW = true 210 )) 211 case SoCParamsKey => up(SoCParamsKey).copy( 212 L3CacheParamsOpt = None 213 ) 214 }) 215) 216 217class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 218 case XSTileKey => 219 val sets = n * 1024 / ways / 64 220 up(XSTileKey).map(_.copy( 221 dcacheParametersOpt = Some(DCacheParameters( 222 nSets = sets, 223 nWays = ways, 224 tagECC = Some("secded"), 225 dataECC = Some("secded"), 226 replacer = Some("setplru"), 227 nMissEntries = 16, 228 nProbeEntries = 8, 229 nReleaseEntries = 18 230 )) 231 )) 232}) 233 234class WithNKBL2 235( 236 n: Int, 237 ways: Int = 8, 238 inclusive: Boolean = true, 239 banks: Int = 1, 240 alwaysReleaseData: Boolean = false 241) extends Config((site, here, up) => { 242 case XSTileKey => 243 val upParams = up(XSTileKey) 244 val l2sets = n * 1024 / banks / ways / 64 245 upParams.map(p => p.copy( 246 L2CacheParamsOpt = Some(HCCacheParameters( 247 name = "L2", 248 level = 2, 249 ways = ways, 250 sets = l2sets, 251 inclusive = inclusive, 252 alwaysReleaseData = alwaysReleaseData, 253 clientCaches = Seq(CacheParameters( 254 "dcache", 255 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 256 ways = p.dcacheParametersOpt.get.nWays + 2, 257 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets / banks), 258 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 259 )), 260 reqField = Seq(PreferCacheField()), 261 echoField = Seq(DirtyField()), 262 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()), 263 enablePerf = true, 264 sramDepthDiv = 2, 265 tagECC = Some("secded"), 266 dataECC = Some("secded"), 267 simulation = !site(DebugOptionsKey).FPGAPlatform 268 )), 269 L2NBanks = banks 270 )) 271}) 272 273class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 274 case SoCParamsKey => 275 val sets = n * 1024 / banks / ways / 64 276 val tiles = site(XSTileKey) 277 val clientDirBytes = tiles.map{ t => 278 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 279 }.sum 280 up(SoCParamsKey).copy( 281 L3NBanks = banks, 282 L3CacheParamsOpt = Some(HCCacheParameters( 283 name = "L3", 284 level = 3, 285 ways = ways, 286 sets = sets, 287 inclusive = inclusive, 288 clientCaches = tiles.map{ core => 289 val l2params = core.L2CacheParamsOpt.get.toCacheParams 290 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 291 }, 292 enablePerf = true, 293 ctrl = Some(CacheCtrl( 294 address = 0x39000000, 295 numCores = tiles.size 296 )), 297 sramClkDivBy2 = true, 298 sramDepthDiv = 4, 299 tagECC = Some("secded"), 300 dataECC = Some("secded"), 301 simulation = !site(DebugOptionsKey).FPGAPlatform 302 )) 303 ) 304}) 305 306class WithL3DebugConfig extends Config( 307 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 308) 309 310class MinimalL3DebugConfig(n: Int = 1) extends Config( 311 new WithL3DebugConfig ++ new MinimalConfig(n) 312) 313 314class DefaultL3DebugConfig(n: Int = 1) extends Config( 315 new WithL3DebugConfig ++ new BaseConfig(n) 316) 317 318class MinimalAliasDebugConfig(n: Int = 1) extends Config( 319 new WithNKBL3(512, inclusive = false) ++ 320 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 321 new WithNKBL1D(128) ++ 322 new MinimalConfig(n) 323) 324 325class MediumConfig(n: Int = 1) extends Config( 326 new WithNKBL3(4096, inclusive = false, banks = 4) 327 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 328 ++ new WithNKBL1D(128) 329 ++ new BaseConfig(n) 330) 331 332class DefaultConfig(n: Int = 1) extends Config( 333 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 334 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 335 ++ new WithNKBL1D(128) 336 ++ new BaseConfig(n) 337) 338