1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import xiangshan.frontend.icache.ICacheParameters 43 44class BaseConfig(n: Int) extends Config((site, here, up) => { 45 case XLen => 64 46 case DebugOptionsKey => DebugOptions() 47 case SoCParamsKey => SoCParameters() 48 case PMParameKey => PMParameters() 49 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 50 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 51 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 52 case JtagDTMKey => JtagDTMKey 53 case MaxHartIdBits => 2 54 case EnableJtag => true.B 55}) 56 57// Synthesizable minimal XiangShan 58// * It is still an out-of-order, super-scalaer arch 59// * L1 cache included 60// * L2 cache NOT included 61// * L3 cache included 62class MinimalConfig(n: Int = 1) extends Config( 63 new BaseConfig(n).alter((site, here, up) => { 64 case XSTileKey => up(XSTileKey).map( 65 _.copy( 66 DecodeWidth = 2, 67 RenameWidth = 2, 68 CommitWidth = 2, 69 FetchWidth = 4, 70 VirtualLoadQueueSize = 24, 71 LoadQueueRARSize = 16, 72 LoadQueueRAWSize = 12, 73 LoadQueueReplaySize = 24, 74 LoadUncacheBufferSize = 8, 75 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 76 RollbackGroupSize = 8, 77 StoreQueueSize = 12, 78 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 79 StoreQueueForwardWithMask = true, 80 RobSize = 32, 81 RabSize = 96, 82 FtqSize = 8, 83 IBufSize = 16, 84 IBufNBank = 2, 85 StoreBufferSize = 4, 86 StoreBufferThreshold = 3, 87 IssueQueueSize = 8, 88 dpParams = DispatchParameters( 89 IntDqSize = 12, 90 FpDqSize = 12, 91 LsDqSize = 12, 92 IntDqDeqWidth = 4, 93 FpDqDeqWidth = 4, 94 LsDqDeqWidth = 6 95 ), 96 intPreg = IntPregParams( 97 numEntries = 64, 98 numRead = None, 99 numWrite = None, 100 ), 101 vfPreg = VfPregParams( 102 numEntries = 160, 103 numRead = Some(14), 104 numWrite = None, 105 ), 106 icacheParameters = ICacheParameters( 107 nSets = 64, // 16KB ICache 108 tagECC = Some("parity"), 109 dataECC = Some("parity"), 110 replacer = Some("setplru"), 111 nMissEntries = 2, 112 nReleaseEntries = 1, 113 nProbeEntries = 2, 114 // fdip 115 enableICachePrefetch = true, 116 prefetchToL1 = false, 117 ), 118 dcacheParametersOpt = Some(DCacheParameters( 119 nSets = 64, // 32KB DCache 120 nWays = 8, 121 tagECC = Some("secded"), 122 dataECC = Some("secded"), 123 replacer = Some("setplru"), 124 nMissEntries = 4, 125 nProbeEntries = 4, 126 nReleaseEntries = 8, 127 nMaxPrefetchEntry = 2, 128 )), 129 EnableBPD = false, // disable TAGE 130 EnableLoop = false, 131 itlbParameters = TLBParameters( 132 name = "itlb", 133 fetchi = true, 134 useDmode = false, 135 NWays = 4, 136 ), 137 ldtlbParameters = TLBParameters( 138 name = "ldtlb", 139 NWays = 4, 140 partialStaticPMP = true, 141 outsideRecvFlush = true, 142 outReplace = false 143 ), 144 sttlbParameters = TLBParameters( 145 name = "sttlb", 146 NWays = 4, 147 partialStaticPMP = true, 148 outsideRecvFlush = true, 149 outReplace = false 150 ), 151 hytlbParameters = TLBParameters( 152 name = "hytlb", 153 NWays = 4, 154 partialStaticPMP = true, 155 outsideRecvFlush = true, 156 outReplace = false 157 ), 158 pftlbParameters = TLBParameters( 159 name = "pftlb", 160 NWays = 4, 161 partialStaticPMP = true, 162 outsideRecvFlush = true, 163 outReplace = false 164 ), 165 btlbParameters = TLBParameters( 166 name = "btlb", 167 NWays = 4, 168 ), 169 l2tlbParameters = L2TLBParameters( 170 l1Size = 4, 171 l2nSets = 4, 172 l2nWays = 4, 173 l3nSets = 4, 174 l3nWays = 8, 175 spSize = 2, 176 ), 177 L2CacheParamsOpt = Some(L2Param( 178 name = "L2", 179 ways = 8, 180 sets = 128, 181 echoField = Seq(huancun.DirtyField()), 182 prefetch = None 183 )), 184 L2NBanks = 2, 185 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 186 ) 187 ) 188 case SoCParamsKey => 189 val tiles = site(XSTileKey) 190 up(SoCParamsKey).copy( 191 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 192 sets = 1024, 193 inclusive = false, 194 clientCaches = tiles.map{ core => 195 val clientDirBytes = tiles.map{ t => 196 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 197 }.sum 198 val l2params = core.L2CacheParamsOpt.get.toCacheParams 199 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 200 }, 201 simulation = !site(DebugOptionsKey).FPGAPlatform, 202 prefetch = None 203 )), 204 L3NBanks = 1 205 ) 206 }) 207) 208 209// Non-synthesizable MinimalConfig, for fast simulation only 210class MinimalSimConfig(n: Int = 1) extends Config( 211 new MinimalConfig(n).alter((site, here, up) => { 212 case XSTileKey => up(XSTileKey).map(_.copy( 213 dcacheParametersOpt = None, 214 softPTW = true 215 )) 216 case SoCParamsKey => up(SoCParamsKey).copy( 217 L3CacheParamsOpt = None 218 ) 219 }) 220) 221 222class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 223 case XSTileKey => 224 val sets = n * 1024 / ways / 64 225 up(XSTileKey).map(_.copy( 226 dcacheParametersOpt = Some(DCacheParameters( 227 nSets = sets, 228 nWays = ways, 229 tagECC = Some("secded"), 230 dataECC = Some("secded"), 231 replacer = Some("setplru"), 232 nMissEntries = 16, 233 nProbeEntries = 8, 234 nReleaseEntries = 18, 235 nMaxPrefetchEntry = 6, 236 )) 237 )) 238}) 239 240class WithNKBL2 241( 242 n: Int, 243 ways: Int = 8, 244 inclusive: Boolean = true, 245 banks: Int = 1 246) extends Config((site, here, up) => { 247 case XSTileKey => 248 require(inclusive, "L2 must be inclusive") 249 val upParams = up(XSTileKey) 250 val l2sets = n * 1024 / banks / ways / 64 251 upParams.map(p => p.copy( 252 L2CacheParamsOpt = Some(L2Param( 253 name = "L2", 254 ways = ways, 255 sets = l2sets, 256 clientCaches = Seq(L1Param( 257 "dcache", 258 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 259 ways = p.dcacheParametersOpt.get.nWays + 2, 260 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 261 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)) 262 )), 263 reqField = Seq(utility.ReqSourceField()), 264 echoField = Seq(huancun.DirtyField()), 265 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()), 266 enablePerf = !site(DebugOptionsKey).FPGAPlatform, 267 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 268 )), 269 L2NBanks = banks 270 )) 271}) 272 273class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 274 case SoCParamsKey => 275 val sets = n * 1024 / banks / ways / 64 276 val tiles = site(XSTileKey) 277 val clientDirBytes = tiles.map{ t => 278 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 279 }.sum 280 up(SoCParamsKey).copy( 281 L3NBanks = banks, 282 L3CacheParamsOpt = Some(HCCacheParameters( 283 name = "L3", 284 level = 3, 285 ways = ways, 286 sets = sets, 287 inclusive = inclusive, 288 clientCaches = tiles.map{ core => 289 val l2params = core.L2CacheParamsOpt.get.toCacheParams 290 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 291 }, 292 enablePerf = true, 293 ctrl = Some(CacheCtrl( 294 address = 0x39000000, 295 numCores = tiles.size 296 )), 297 reqField = Seq(utility.ReqSourceField()), 298 sramClkDivBy2 = true, 299 sramDepthDiv = 4, 300 tagECC = Some("secded"), 301 dataECC = Some("secded"), 302 simulation = !site(DebugOptionsKey).FPGAPlatform, 303 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 304 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 305 )) 306 ) 307}) 308 309class WithL3DebugConfig extends Config( 310 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 311) 312 313class MinimalL3DebugConfig(n: Int = 1) extends Config( 314 new WithL3DebugConfig ++ new MinimalConfig(n) 315) 316 317class DefaultL3DebugConfig(n: Int = 1) extends Config( 318 new WithL3DebugConfig ++ new BaseConfig(n) 319) 320 321class WithFuzzer extends Config((site, here, up) => { 322 case DebugOptionsKey => up(DebugOptionsKey).copy( 323 EnablePerfDebug = false, 324 ) 325 case SoCParamsKey => up(SoCParamsKey).copy( 326 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 327 enablePerf = false, 328 )), 329 ) 330 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 331 p.copy( 332 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 333 enablePerf = false, 334 )), 335 ) 336 } 337}) 338 339class MinimalAliasDebugConfig(n: Int = 1) extends Config( 340 new WithNKBL3(512, inclusive = false) ++ 341 new WithNKBL2(256, inclusive = true) ++ 342 new WithNKBL1D(128) ++ 343 new MinimalConfig(n) 344) 345 346class MediumConfig(n: Int = 1) extends Config( 347 new WithNKBL3(4096, inclusive = false, banks = 4) 348 ++ new WithNKBL2(512, inclusive = true) 349 ++ new WithNKBL1D(128) 350 ++ new BaseConfig(n) 351) 352 353class FuzzConfig(dummy: Int = 0) extends Config( 354 new WithFuzzer 355 ++ new DefaultConfig(1) 356) 357 358class DefaultConfig(n: Int = 1) extends Config( 359 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 360 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 361 ++ new WithNKBL1D(64, ways = 4) 362 ++ new BaseConfig(n) 363) 364