1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import chipsalliance.rocketchip.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.MaxHartIdBits 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.exu.ExuParameters 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36import coupledL2._ 37 38class BaseConfig(n: Int) extends Config((site, here, up) => { 39 case XLen => 64 40 case DebugOptionsKey => DebugOptions() 41 case SoCParamsKey => SoCParameters() 42 case PMParameKey => PMParameters() 43 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 44 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 45 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 46 case JtagDTMKey => JtagDTMKey 47 case MaxHartIdBits => 2 48 case EnableJtag => true.B 49}) 50 51// Synthesizable minimal XiangShan 52// * It is still an out-of-order, super-scalaer arch 53// * L1 cache included 54// * L2 cache NOT included 55// * L3 cache included 56class MinimalConfig(n: Int = 1) extends Config( 57 new BaseConfig(n).alter((site, here, up) => { 58 case XSTileKey => up(XSTileKey).map( 59 _.copy( 60 DecodeWidth = 2, 61 RenameWidth = 2, 62 CommitWidth = 2, 63 FetchWidth = 4, 64 IssQueSize = 8, 65 NRPhyRegs = 64, 66 VirtualLoadQueueSize = 16, 67 LoadQueueRARSize = 16, 68 LoadQueueRAWSize = 12, 69 LoadQueueReplaySize = 8, 70 LoadUncacheBufferSize = 8, 71 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 72 RollbackGroupSize = 8, 73 StoreQueueSize = 12, 74 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 75 StoreQueueForwardWithMask = true, 76 RobSize = 32, 77 FtqSize = 8, 78 IBufSize = 16, 79 StoreBufferSize = 4, 80 StoreBufferThreshold = 3, 81 dpParams = DispatchParameters( 82 IntDqSize = 12, 83 FpDqSize = 12, 84 LsDqSize = 12, 85 IntDqDeqWidth = 4, 86 FpDqDeqWidth = 4, 87 LsDqDeqWidth = 4 88 ), 89 exuParameters = ExuParameters( 90 JmpCnt = 1, 91 AluCnt = 2, 92 MulCnt = 0, 93 MduCnt = 1, 94 FmacCnt = 1, 95 FmiscCnt = 1, 96 FmiscDivSqrtCnt = 0, 97 LduCnt = 2, 98 StuCnt = 2 99 ), 100 icacheParameters = ICacheParameters( 101 nSets = 64, // 16KB ICache 102 tagECC = Some("parity"), 103 dataECC = Some("parity"), 104 replacer = Some("setplru"), 105 nMissEntries = 2, 106 nReleaseEntries = 1, 107 nProbeEntries = 2, 108 nPrefetchEntries = 2, 109 nPrefBufferEntries = 32, 110 hasPrefetch = true 111 ), 112 dcacheParametersOpt = Some(DCacheParameters( 113 nSets = 64, // 32KB DCache 114 nWays = 8, 115 tagECC = Some("secded"), 116 dataECC = Some("secded"), 117 replacer = Some("setplru"), 118 nMissEntries = 4, 119 nProbeEntries = 4, 120 nReleaseEntries = 8, 121 nMaxPrefetchEntry = 2, 122 )), 123 EnableBPD = false, // disable TAGE 124 EnableLoop = false, 125 itlbParameters = TLBParameters( 126 name = "itlb", 127 fetchi = true, 128 useDmode = false, 129 normalReplacer = Some("plru"), 130 superReplacer = Some("plru"), 131 normalNWays = 4, 132 normalNSets = 1, 133 superNWays = 2 134 ), 135 ldtlbParameters = TLBParameters( 136 name = "ldtlb", 137 normalNSets = 16, // when da or sa 138 normalNWays = 1, // when fa or sa 139 normalAssociative = "sa", 140 normalReplacer = Some("setplru"), 141 superNWays = 4, 142 normalAsVictim = true, 143 partialStaticPMP = true, 144 outsideRecvFlush = true, 145 outReplace = false 146 ), 147 sttlbParameters = TLBParameters( 148 name = "sttlb", 149 normalNSets = 16, // when da or sa 150 normalNWays = 1, // when fa or sa 151 normalAssociative = "sa", 152 normalReplacer = Some("setplru"), 153 normalAsVictim = true, 154 superNWays = 4, 155 partialStaticPMP = true, 156 outsideRecvFlush = true, 157 outReplace = false 158 ), 159 pftlbParameters = TLBParameters( 160 name = "pftlb", 161 normalNSets = 16, // when da or sa 162 normalNWays = 1, // when fa or sa 163 normalAssociative = "sa", 164 normalReplacer = Some("setplru"), 165 normalAsVictim = true, 166 superNWays = 4, 167 partialStaticPMP = true, 168 outsideRecvFlush = true, 169 outReplace = false 170 ), 171 btlbParameters = TLBParameters( 172 name = "btlb", 173 normalNSets = 1, 174 normalNWays = 8, 175 superNWays = 2 176 ), 177 l2tlbParameters = L2TLBParameters( 178 l1Size = 4, 179 l2nSets = 4, 180 l2nWays = 4, 181 l3nSets = 4, 182 l3nWays = 8, 183 spSize = 2, 184 ), 185 L2CacheParamsOpt = Some(L2Param( 186 name = "L2", 187 ways = 8, 188 sets = 128, 189 echoField = Seq(huancun.DirtyField()), 190 prefetch = None 191 )), 192 L2NBanks = 2, 193 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 194 ) 195 ) 196 case SoCParamsKey => 197 val tiles = site(XSTileKey) 198 up(SoCParamsKey).copy( 199 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 200 sets = 1024, 201 inclusive = false, 202 clientCaches = tiles.map{ core => 203 val clientDirBytes = tiles.map{ t => 204 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 205 }.sum 206 val l2params = core.L2CacheParamsOpt.get.toCacheParams 207 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 208 }, 209 simulation = !site(DebugOptionsKey).FPGAPlatform, 210 prefetch = None 211 )), 212 L3NBanks = 1 213 ) 214 }) 215) 216 217// Non-synthesizable MinimalConfig, for fast simulation only 218class MinimalSimConfig(n: Int = 1) extends Config( 219 new MinimalConfig(n).alter((site, here, up) => { 220 case XSTileKey => up(XSTileKey).map(_.copy( 221 dcacheParametersOpt = None, 222 softPTW = true 223 )) 224 case SoCParamsKey => up(SoCParamsKey).copy( 225 L3CacheParamsOpt = None 226 ) 227 }) 228) 229 230class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 231 case XSTileKey => 232 val sets = n * 1024 / ways / 64 233 up(XSTileKey).map(_.copy( 234 dcacheParametersOpt = Some(DCacheParameters( 235 nSets = sets, 236 nWays = ways, 237 tagECC = Some("secded"), 238 dataECC = Some("secded"), 239 replacer = Some("setplru"), 240 nMissEntries = 16, 241 nProbeEntries = 8, 242 nReleaseEntries = 18, 243 nMaxPrefetchEntry = 6, 244 )) 245 )) 246}) 247 248class WithNKBL2 249( 250 n: Int, 251 ways: Int = 8, 252 inclusive: Boolean = true, 253 banks: Int = 1 254) extends Config((site, here, up) => { 255 case XSTileKey => 256 val upParams = up(XSTileKey) 257 val l2sets = n * 1024 / banks / ways / 64 258 upParams.map(p => p.copy( 259 L2CacheParamsOpt = Some(L2Param( 260 name = "L2", 261 ways = ways, 262 sets = l2sets, 263 clientCaches = Seq(L1Param( 264 "dcache", 265 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 266 ways = p.dcacheParametersOpt.get.nWays + 2, 267 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 268 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)) 269 )), 270 reqField = Seq(utility.ReqSourceField()), 271 echoField = Seq(huancun.DirtyField()), 272 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 273 )), 274 L2NBanks = banks 275 )) 276}) 277 278class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 279 case SoCParamsKey => 280 val sets = n * 1024 / banks / ways / 64 281 val tiles = site(XSTileKey) 282 val clientDirBytes = tiles.map{ t => 283 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 284 }.sum 285 up(SoCParamsKey).copy( 286 L3NBanks = banks, 287 L3CacheParamsOpt = Some(HCCacheParameters( 288 name = "L3", 289 level = 3, 290 ways = ways, 291 sets = sets, 292 inclusive = inclusive, 293 clientCaches = tiles.map{ core => 294 val l2params = core.L2CacheParamsOpt.get.toCacheParams 295 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 296 }, 297 enablePerf = true, 298 ctrl = Some(CacheCtrl( 299 address = 0x39000000, 300 numCores = tiles.size 301 )), 302 reqField = Seq(utility.ReqSourceField()), 303 sramClkDivBy2 = true, 304 sramDepthDiv = 4, 305 tagECC = Some("secded"), 306 dataECC = Some("secded"), 307 simulation = !site(DebugOptionsKey).FPGAPlatform, 308 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()) 309 )) 310 ) 311}) 312 313class WithL3DebugConfig extends Config( 314 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 315) 316 317class MinimalL3DebugConfig(n: Int = 1) extends Config( 318 new WithL3DebugConfig ++ new MinimalConfig(n) 319) 320 321class DefaultL3DebugConfig(n: Int = 1) extends Config( 322 new WithL3DebugConfig ++ new BaseConfig(n) 323) 324 325class WithFuzzer extends Config((site, here, up) => { 326 case DebugOptionsKey => up(DebugOptionsKey).copy( 327 EnablePerfDebug = false, 328 ) 329 case SoCParamsKey => up(SoCParamsKey).copy( 330 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 331 enablePerf = false, 332 )), 333 ) 334 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 335 p.copy( 336 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 337 enablePerf = false, 338 )), 339 ) 340 } 341}) 342 343class MinimalAliasDebugConfig(n: Int = 1) extends Config( 344 new WithNKBL3(512, inclusive = false) ++ 345 new WithNKBL2(256, inclusive = false) ++ 346 new WithNKBL1D(128) ++ 347 new MinimalConfig(n) 348) 349 350class MediumConfig(n: Int = 1) extends Config( 351 new WithNKBL3(4096, inclusive = false, banks = 4) 352 ++ new WithNKBL2(512, inclusive = false) 353 ++ new WithNKBL1D(128) 354 ++ new BaseConfig(n) 355) 356 357class FuzzConfig(dummy: Int = 0) extends Config( 358 new WithFuzzer 359 ++ new DefaultConfig(1) 360) 361 362class DefaultConfig(n: Int = 1) extends Config( 363 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 364 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4) 365 ++ new WithNKBL1D(128) 366 ++ new BaseConfig(n) 367) 368