1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.MaxHartIdBits 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.exu.ExuParameters 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36import coupledL2._ 37 38class BaseConfig(n: Int) extends Config((site, here, up) => { 39 case XLen => 64 40 case DebugOptionsKey => DebugOptions() 41 case SoCParamsKey => SoCParameters() 42 case PMParameKey => PMParameters() 43 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 44 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 45 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 46 case JtagDTMKey => JtagDTMKey 47 case MaxHartIdBits => 2 48 case EnableJtag => true.B 49}) 50 51// Synthesizable minimal XiangShan 52// * It is still an out-of-order, super-scalaer arch 53// * L1 cache included 54// * L2 cache NOT included 55// * L3 cache included 56class MinimalConfig(n: Int = 1) extends Config( 57 new BaseConfig(n).alter((site, here, up) => { 58 case XSTileKey => up(XSTileKey).map( 59 p => p.copy( 60 DecodeWidth = 2, 61 RenameWidth = 2, 62 CommitWidth = 2, 63 FetchWidth = 4, 64 IssQueSize = 8, 65 NRPhyRegs = 64, 66 VirtualLoadQueueSize = 16, 67 LoadQueueRARSize = 16, 68 LoadQueueRAWSize = 12, 69 LoadQueueReplaySize = 8, 70 LoadUncacheBufferSize = 8, 71 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 72 RollbackGroupSize = 8, 73 StoreQueueSize = 12, 74 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 75 StoreQueueForwardWithMask = true, 76 RobSize = 32, 77 FtqSize = 8, 78 IBufSize = 16, 79 IBufNBank = 2, 80 StoreBufferSize = 4, 81 StoreBufferThreshold = 3, 82 dpParams = DispatchParameters( 83 IntDqSize = 12, 84 FpDqSize = 12, 85 LsDqSize = 12, 86 IntDqDeqWidth = 4, 87 FpDqDeqWidth = 4, 88 LsDqDeqWidth = 4 89 ), 90 exuParameters = ExuParameters( 91 JmpCnt = 1, 92 AluCnt = 2, 93 MulCnt = 0, 94 MduCnt = 1, 95 FmacCnt = 1, 96 FmiscCnt = 1, 97 FmiscDivSqrtCnt = 0, 98 LduCnt = 2, 99 StuCnt = 2 100 ), 101 icacheParameters = ICacheParameters( 102 nSets = 64, // 16KB ICache 103 tagECC = Some("parity"), 104 dataECC = Some("parity"), 105 replacer = Some("setplru"), 106 nMissEntries = 2, 107 nReleaseEntries = 1, 108 nProbeEntries = 2, 109 // fdip 110 enableICachePrefetch = true, 111 prefetchToL1 = false, 112 ), 113 dcacheParametersOpt = Some(DCacheParameters( 114 nSets = 64, // 32KB DCache 115 nWays = 8, 116 tagECC = Some("secded"), 117 dataECC = Some("secded"), 118 replacer = Some("setplru"), 119 nMissEntries = 4, 120 nProbeEntries = 4, 121 nReleaseEntries = 8, 122 nMaxPrefetchEntry = 2, 123 )), 124 EnableBPD = false, // disable TAGE 125 EnableLoop = false, 126 itlbParameters = TLBParameters( 127 name = "itlb", 128 fetchi = true, 129 useDmode = false, 130 NWays = 4, 131 ), 132 ldtlbParameters = TLBParameters( 133 name = "ldtlb", 134 NWays = 4, 135 partialStaticPMP = true, 136 outsideRecvFlush = true, 137 outReplace = false 138 ), 139 sttlbParameters = TLBParameters( 140 name = "sttlb", 141 NWays = 4, 142 partialStaticPMP = true, 143 outsideRecvFlush = true, 144 outReplace = false 145 ), 146 pftlbParameters = TLBParameters( 147 name = "pftlb", 148 NWays = 4, 149 partialStaticPMP = true, 150 outsideRecvFlush = true, 151 outReplace = false 152 ), 153 btlbParameters = TLBParameters( 154 name = "btlb", 155 NWays = 4, 156 ), 157 l2tlbParameters = L2TLBParameters( 158 l1Size = 4, 159 l2nSets = 4, 160 l2nWays = 4, 161 l3nSets = 4, 162 l3nWays = 8, 163 spSize = 2, 164 ), 165 L2CacheParamsOpt = Some(L2Param( 166 name = "L2", 167 ways = 8, 168 sets = 128, 169 echoField = Seq(huancun.DirtyField()), 170 prefetch = None, 171 clientCaches = Seq(L1Param( 172 "dcache", 173 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 174 )), 175 ) 176 ), 177 L2NBanks = 2, 178 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 179 ) 180 ) 181 case SoCParamsKey => 182 val tiles = site(XSTileKey) 183 up(SoCParamsKey).copy( 184 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 185 sets = 1024, 186 inclusive = false, 187 clientCaches = tiles.map{ core => 188 val clientDirBytes = tiles.map{ t => 189 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 190 }.sum 191 val l2params = core.L2CacheParamsOpt.get.toCacheParams 192 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 193 }, 194 simulation = !site(DebugOptionsKey).FPGAPlatform, 195 prefetch = None 196 )), 197 L3NBanks = 1 198 ) 199 }) 200) 201 202// Non-synthesizable MinimalConfig, for fast simulation only 203class MinimalSimConfig(n: Int = 1) extends Config( 204 new MinimalConfig(n).alter((site, here, up) => { 205 case XSTileKey => up(XSTileKey).map(_.copy( 206 dcacheParametersOpt = None, 207 softPTW = true 208 )) 209 case SoCParamsKey => up(SoCParamsKey).copy( 210 L3CacheParamsOpt = None 211 ) 212 }) 213) 214 215class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 216 case XSTileKey => 217 val sets = n * 1024 / ways / 64 218 up(XSTileKey).map(_.copy( 219 dcacheParametersOpt = Some(DCacheParameters( 220 nSets = sets, 221 nWays = ways, 222 tagECC = Some("secded"), 223 dataECC = Some("secded"), 224 replacer = Some("setplru"), 225 nMissEntries = 16, 226 nProbeEntries = 8, 227 nReleaseEntries = 18, 228 nMaxPrefetchEntry = 6, 229 )) 230 )) 231}) 232 233class WithNKBL2 234( 235 n: Int, 236 ways: Int = 8, 237 inclusive: Boolean = true, 238 banks: Int = 1 239) extends Config((site, here, up) => { 240 case XSTileKey => 241 require(inclusive, "L2 must be inclusive") 242 val upParams = up(XSTileKey) 243 val l2sets = n * 1024 / banks / ways / 64 244 upParams.map(p => p.copy( 245 L2CacheParamsOpt = Some(L2Param( 246 name = "L2", 247 ways = ways, 248 sets = l2sets, 249 clientCaches = Seq(L1Param( 250 "dcache", 251 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 252 ways = p.dcacheParametersOpt.get.nWays + 2, 253 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 254 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)), 255 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 256 )), 257 reqField = Seq(utility.ReqSourceField()), 258 echoField = Seq(huancun.DirtyField()), 259 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()), 260 enablePerf = !site(DebugOptionsKey).FPGAPlatform, 261 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 262 )), 263 L2NBanks = banks 264 )) 265}) 266 267class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 268 case SoCParamsKey => 269 val sets = n * 1024 / banks / ways / 64 270 val tiles = site(XSTileKey) 271 val clientDirBytes = tiles.map{ t => 272 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 273 }.sum 274 up(SoCParamsKey).copy( 275 L3NBanks = banks, 276 L3CacheParamsOpt = Some(HCCacheParameters( 277 name = "L3", 278 level = 3, 279 ways = ways, 280 sets = sets, 281 inclusive = inclusive, 282 clientCaches = tiles.map{ core => 283 val l2params = core.L2CacheParamsOpt.get.toCacheParams 284 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 285 }, 286 enablePerf = true, 287 ctrl = Some(CacheCtrl( 288 address = 0x39000000, 289 numCores = tiles.size 290 )), 291 reqField = Seq(utility.ReqSourceField()), 292 sramClkDivBy2 = true, 293 sramDepthDiv = 4, 294 tagECC = Some("secded"), 295 dataECC = Some("secded"), 296 simulation = !site(DebugOptionsKey).FPGAPlatform, 297 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 298 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 299 )) 300 ) 301}) 302 303class WithL3DebugConfig extends Config( 304 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 305) 306 307class MinimalL3DebugConfig(n: Int = 1) extends Config( 308 new WithL3DebugConfig ++ new MinimalConfig(n) 309) 310 311class DefaultL3DebugConfig(n: Int = 1) extends Config( 312 new WithL3DebugConfig ++ new BaseConfig(n) 313) 314 315class WithFuzzer extends Config((site, here, up) => { 316 case DebugOptionsKey => up(DebugOptionsKey).copy( 317 EnablePerfDebug = false, 318 ) 319 case SoCParamsKey => up(SoCParamsKey).copy( 320 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 321 enablePerf = false, 322 )), 323 ) 324 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 325 p.copy( 326 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 327 enablePerf = false, 328 )), 329 ) 330 } 331}) 332 333class MinimalAliasDebugConfig(n: Int = 1) extends Config( 334 new WithNKBL3(512, inclusive = false) ++ 335 new WithNKBL2(256, inclusive = true) ++ 336 new WithNKBL1D(128) ++ 337 new MinimalConfig(n) 338) 339 340class MediumConfig(n: Int = 1) extends Config( 341 new WithNKBL3(4096, inclusive = false, banks = 4) 342 ++ new WithNKBL2(512, inclusive = true) 343 ++ new WithNKBL1D(128) 344 ++ new BaseConfig(n) 345) 346 347class FuzzConfig(dummy: Int = 0) extends Config( 348 new WithFuzzer 349 ++ new DefaultConfig(1) 350) 351 352class DefaultConfig(n: Int = 1) extends Config( 353 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 354 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 355 ++ new WithNKBL1D(64, ways = 4) 356 ++ new BaseConfig(n) 357) 358