1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import xiangshan.frontend.icache.ICacheParameters 27import freechips.rocketchip.devices.debug._ 28import freechips.rocketchip.tile.MaxHartIdBits 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.backend.exu.ExuParameters 31import xiangshan.cache.DCacheParameters 32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 33import device.{EnableJtag, XSDebugModuleParams} 34import huancun._ 35 36class BaseConfig(n: Int) extends Config((site, here, up) => { 37 case XLen => 64 38 case DebugOptionsKey => DebugOptions() 39 case SoCParamsKey => SoCParameters() 40 case PMParameKey => PMParameters() 41 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 42 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 43 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 44 case JtagDTMKey => JtagDTMKey 45 case MaxHartIdBits => 2 46 case EnableJtag => true.B 47}) 48 49// Synthesizable minimal XiangShan 50// * It is still an out-of-order, super-scalaer arch 51// * L1 cache included 52// * L2 cache NOT included 53// * L3 cache included 54class MinimalConfig(n: Int = 1) extends Config( 55 new BaseConfig(n).alter((site, here, up) => { 56 case XSTileKey => up(XSTileKey).map( 57 _.copy( 58 DecodeWidth = 2, 59 RenameWidth = 2, 60 CommitWidth = 2, 61 FetchWidth = 4, 62 IssQueSize = 8, 63 NRPhyRegs = 64, 64 LoadQueueSize = 16, 65 StoreQueueSize = 12, 66 RobSize = 32, 67 FtqSize = 8, 68 IBufSize = 16, 69 StoreBufferSize = 4, 70 StoreBufferThreshold = 3, 71 dpParams = DispatchParameters( 72 IntDqSize = 12, 73 FpDqSize = 12, 74 LsDqSize = 12, 75 IntDqDeqWidth = 4, 76 FpDqDeqWidth = 4, 77 LsDqDeqWidth = 4 78 ), 79 exuParameters = ExuParameters( 80 JmpCnt = 1, 81 AluCnt = 2, 82 MulCnt = 0, 83 MduCnt = 1, 84 FmacCnt = 1, 85 FmiscCnt = 1, 86 FmiscDivSqrtCnt = 0, 87 LduCnt = 2, 88 StuCnt = 2 89 ), 90 icacheParameters = ICacheParameters( 91 nSets = 64, // 16KB ICache 92 tagECC = Some("parity"), 93 dataECC = Some("parity"), 94 replacer = Some("setplru"), 95 nMissEntries = 2, 96 nReleaseEntries = 1, 97 nProbeEntries = 2, 98 nPrefetchEntries = 2, 99 hasPrefetch = false 100 ), 101 dcacheParametersOpt = Some(DCacheParameters( 102 nSets = 64, // 32KB DCache 103 nWays = 8, 104 tagECC = Some("secded"), 105 dataECC = Some("secded"), 106 replacer = Some("setplru"), 107 nMissEntries = 4, 108 nProbeEntries = 4, 109 nReleaseEntries = 8, 110 )), 111 EnableBPD = false, // disable TAGE 112 EnableLoop = false, 113 itlbParameters = TLBParameters( 114 name = "itlb", 115 fetchi = true, 116 useDmode = false, 117 normalReplacer = Some("plru"), 118 superReplacer = Some("plru"), 119 normalNWays = 4, 120 normalNSets = 1, 121 superNWays = 2 122 ), 123 ldtlbParameters = TLBParameters( 124 name = "ldtlb", 125 normalNSets = 16, // when da or sa 126 normalNWays = 1, // when fa or sa 127 normalAssociative = "sa", 128 normalReplacer = Some("setplru"), 129 superNWays = 4, 130 normalAsVictim = true, 131 partialStaticPMP = true, 132 outsideRecvFlush = true, 133 outReplace = false 134 ), 135 sttlbParameters = TLBParameters( 136 name = "sttlb", 137 normalNSets = 16, // when da or sa 138 normalNWays = 1, // when fa or sa 139 normalAssociative = "sa", 140 normalReplacer = Some("setplru"), 141 normalAsVictim = true, 142 superNWays = 4, 143 partialStaticPMP = true, 144 outsideRecvFlush = true, 145 outReplace = false 146 ), 147 btlbParameters = TLBParameters( 148 name = "btlb", 149 normalNSets = 1, 150 normalNWays = 8, 151 superNWays = 2 152 ), 153 l2tlbParameters = L2TLBParameters( 154 l1Size = 4, 155 l2nSets = 4, 156 l2nWays = 4, 157 l3nSets = 4, 158 l3nWays = 8, 159 spSize = 2, 160 ), 161 L2CacheParamsOpt = None // remove L2 Cache 162 ) 163 ) 164 case SoCParamsKey => 165 val tiles = site(XSTileKey) 166 up(SoCParamsKey).copy( 167 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 168 sets = 1024, 169 inclusive = false, 170 clientCaches = tiles.map{ p => 171 CacheParameters( 172 "dcache", 173 sets = 2 * p.dcacheParametersOpt.get.nSets, 174 ways = p.dcacheParametersOpt.get.nWays + 2, 175 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets), 176 aliasBitsOpt = None 177 ) 178 }, 179 simulation = !site(DebugOptionsKey).FPGAPlatform 180 )), 181 L3NBanks = 1 182 ) 183 }) 184) 185 186// Non-synthesizable MinimalConfig, for fast simulation only 187class MinimalSimConfig(n: Int = 1) extends Config( 188 new MinimalConfig(n).alter((site, here, up) => { 189 case XSTileKey => up(XSTileKey).map(_.copy( 190 dcacheParametersOpt = None, 191 softPTW = true 192 )) 193 case SoCParamsKey => up(SoCParamsKey).copy( 194 L3CacheParamsOpt = None 195 ) 196 }) 197) 198 199class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 200 case XSTileKey => 201 val sets = n * 1024 / ways / 64 202 up(XSTileKey).map(_.copy( 203 dcacheParametersOpt = Some(DCacheParameters( 204 nSets = sets, 205 nWays = ways, 206 tagECC = Some("secded"), 207 dataECC = Some("secded"), 208 replacer = Some("setplru"), 209 nMissEntries = 16, 210 nProbeEntries = 8, 211 nReleaseEntries = 18 212 )) 213 )) 214}) 215 216class WithNKBL2 217( 218 n: Int, 219 ways: Int = 8, 220 inclusive: Boolean = true, 221 banks: Int = 1, 222 alwaysReleaseData: Boolean = false 223) extends Config((site, here, up) => { 224 case XSTileKey => 225 val upParams = up(XSTileKey) 226 val l2sets = n * 1024 / banks / ways / 64 227 upParams.map(p => p.copy( 228 L2CacheParamsOpt = Some(HCCacheParameters( 229 name = "L2", 230 level = 2, 231 ways = ways, 232 sets = l2sets, 233 inclusive = inclusive, 234 alwaysReleaseData = alwaysReleaseData, 235 clientCaches = Seq(CacheParameters( 236 "dcache", 237 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 238 ways = p.dcacheParametersOpt.get.nWays + 2, 239 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets / banks), 240 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 241 )), 242 reqField = Seq(PreferCacheField()), 243 echoField = Seq(DirtyField()), 244 prefetch = Some(huancun.prefetch.BOPParameters()), 245 enablePerf = true, 246 sramDepthDiv = 2, 247 tagECC = Some("secded"), 248 dataECC = Some("secded"), 249 simulation = !site(DebugOptionsKey).FPGAPlatform 250 )), 251 L2NBanks = banks 252 )) 253}) 254 255class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 256 case SoCParamsKey => 257 val sets = n * 1024 / banks / ways / 64 258 val tiles = site(XSTileKey) 259 val clientDirBytes = tiles.map{ t => 260 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 261 }.sum 262 up(SoCParamsKey).copy( 263 L3NBanks = banks, 264 L3CacheParamsOpt = Some(HCCacheParameters( 265 name = "L3", 266 level = 3, 267 ways = ways, 268 sets = sets, 269 inclusive = inclusive, 270 clientCaches = tiles.map{ core => 271 val l2params = core.L2CacheParamsOpt.get.toCacheParams 272 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 273 }, 274 enablePerf = true, 275 ctrl = Some(CacheCtrl( 276 address = 0x39000000, 277 numCores = tiles.size 278 )), 279 sramClkDivBy2 = true, 280 sramDepthDiv = 4, 281 tagECC = Some("secded"), 282 dataECC = Some("secded"), 283 simulation = !site(DebugOptionsKey).FPGAPlatform 284 )) 285 ) 286}) 287 288class WithL3DebugConfig extends Config( 289 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 290) 291 292class MinimalL3DebugConfig(n: Int = 1) extends Config( 293 new WithL3DebugConfig ++ new MinimalConfig(n) 294) 295 296class DefaultL3DebugConfig(n: Int = 1) extends Config( 297 new WithL3DebugConfig ++ new BaseConfig(n) 298) 299 300class MinimalAliasDebugConfig(n: Int = 1) extends Config( 301 new WithNKBL3(512, inclusive = false) ++ 302 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 303 new WithNKBL1D(128) ++ 304 new MinimalConfig(n) 305) 306 307class MediumConfig(n: Int = 1) extends Config( 308 new WithNKBL3(4096, inclusive = false, banks = 4) 309 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 310 ++ new WithNKBL1D(128) 311 ++ new BaseConfig(n) 312) 313 314class DefaultConfig(n: Int = 1) extends Config( 315 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 316 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 317 ++ new WithNKBL1D(128) 318 ++ new BaseConfig(n) 319) 320