1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config._ 20import chisel3._ 21import chisel3.util._ 22import device.{EnableJtag, XSDebugModuleParams} 23import freechips.rocketchip.devices.debug._ 24import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 25import system._ 26import utility._ 27import utils._ 28import huancun._ 29import xiangshan._ 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36import coupledL2._ 37import xiangshan.frontend.icache.ICacheParameters 38 39class BaseConfig(n: Int) extends Config((site, here, up) => { 40 case XLen => 64 41 case DebugOptionsKey => DebugOptions() 42 case SoCParamsKey => SoCParameters() 43 case PMParameKey => PMParameters() 44 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 45 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 46 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 47 case JtagDTMKey => JtagDTMKey 48 case MaxHartIdBits => 2 49 case EnableJtag => true.B 50}) 51 52// Synthesizable minimal XiangShan 53// * It is still an out-of-order, super-scalaer arch 54// * L1 cache included 55// * L2 cache NOT included 56// * L3 cache included 57class MinimalConfig(n: Int = 1) extends Config( 58 new BaseConfig(n).alter((site, here, up) => { 59 case XSTileKey => up(XSTileKey).map( 60 _.copy( 61 DecodeWidth = 2, 62 RenameWidth = 2, 63 CommitWidth = 2, 64 FetchWidth = 4, 65 VirtualLoadQueueSize = 16, 66 LoadQueueRARSize = 16, 67 LoadQueueRAWSize = 12, 68 LoadQueueReplaySize = 8, 69 LoadUncacheBufferSize = 8, 70 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 71 RollbackGroupSize = 8, 72 StoreQueueSize = 12, 73 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 74 StoreQueueForwardWithMask = true, 75 RobSize = 32, 76 RabSize = 32, 77 FtqSize = 8, 78 IBufSize = 16, 79 StoreBufferSize = 4, 80 StoreBufferThreshold = 3, 81 dpParams = DispatchParameters( 82 IntDqSize = 12, 83 FpDqSize = 12, 84 LsDqSize = 12, 85 IntDqDeqWidth = 4, 86 FpDqDeqWidth = 4, 87 LsDqDeqWidth = 4 88 ), 89 intPreg = IntPregParams( 90 numEntries = 64, 91 numRead = Some(14), 92 numWrite = Some(8), 93 ), 94 vfPreg = VfPregParams( 95 numEntries = 96, 96 numRead = Some(14), 97 numWrite = Some(8), 98 ), 99 icacheParameters = ICacheParameters( 100 nSets = 64, // 16KB ICache 101 tagECC = Some("parity"), 102 dataECC = Some("parity"), 103 replacer = Some("setplru"), 104 nMissEntries = 2, 105 nReleaseEntries = 1, 106 nProbeEntries = 2, 107 nPrefetchEntries = 2, 108 nPrefBufferEntries = 32, 109 hasPrefetch = true 110 ), 111 dcacheParametersOpt = Some(DCacheParameters( 112 nSets = 64, // 32KB DCache 113 nWays = 8, 114 tagECC = Some("secded"), 115 dataECC = Some("secded"), 116 replacer = Some("setplru"), 117 nMissEntries = 4, 118 nProbeEntries = 4, 119 nReleaseEntries = 8, 120 )), 121 EnableBPD = false, // disable TAGE 122 EnableLoop = false, 123 itlbParameters = TLBParameters( 124 name = "itlb", 125 fetchi = true, 126 useDmode = false, 127 normalReplacer = Some("plru"), 128 superReplacer = Some("plru"), 129 normalNWays = 4, 130 normalNSets = 1, 131 superNWays = 2 132 ), 133 ldtlbParameters = TLBParameters( 134 name = "ldtlb", 135 normalNSets = 16, // when da or sa 136 normalNWays = 1, // when fa or sa 137 normalAssociative = "sa", 138 normalReplacer = Some("setplru"), 139 superNWays = 4, 140 normalAsVictim = true, 141 partialStaticPMP = true, 142 outsideRecvFlush = true, 143 outReplace = false 144 ), 145 sttlbParameters = TLBParameters( 146 name = "sttlb", 147 normalNSets = 16, // when da or sa 148 normalNWays = 1, // when fa or sa 149 normalAssociative = "sa", 150 normalReplacer = Some("setplru"), 151 normalAsVictim = true, 152 superNWays = 4, 153 partialStaticPMP = true, 154 outsideRecvFlush = true, 155 outReplace = false 156 ), 157 pftlbParameters = TLBParameters( 158 name = "pftlb", 159 normalNSets = 16, // when da or sa 160 normalNWays = 1, // when fa or sa 161 normalAssociative = "sa", 162 normalReplacer = Some("setplru"), 163 normalAsVictim = true, 164 superNWays = 4, 165 partialStaticPMP = true, 166 outsideRecvFlush = true, 167 outReplace = false 168 ), 169 btlbParameters = TLBParameters( 170 name = "btlb", 171 normalNSets = 1, 172 normalNWays = 8, 173 superNWays = 2 174 ), 175 l2tlbParameters = L2TLBParameters( 176 l1Size = 4, 177 l2nSets = 4, 178 l2nWays = 4, 179 l3nSets = 4, 180 l3nWays = 8, 181 spSize = 2, 182 ), 183 L2CacheParamsOpt = Some(L2Param( 184 name = "L2", 185 ways = 8, 186 sets = 128, 187 echoField = Seq(huancun.DirtyField()), 188 prefetch = None 189 )), 190 L2NBanks = 2, 191 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 192 ) 193 ) 194 case SoCParamsKey => 195 val tiles = site(XSTileKey) 196 up(SoCParamsKey).copy( 197 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 198 sets = 1024, 199 inclusive = false, 200 clientCaches = tiles.map{ core => 201 val clientDirBytes = tiles.map{ t => 202 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 203 }.sum 204 val l2params = core.L2CacheParamsOpt.get.toCacheParams 205 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 206 }, 207 simulation = !site(DebugOptionsKey).FPGAPlatform 208 )), 209 L3NBanks = 1 210 ) 211 }) 212) 213 214// Non-synthesizable MinimalConfig, for fast simulation only 215class MinimalSimConfig(n: Int = 1) extends Config( 216 new MinimalConfig(n).alter((site, here, up) => { 217 case XSTileKey => up(XSTileKey).map(_.copy( 218 dcacheParametersOpt = None, 219 softPTW = true 220 )) 221 case SoCParamsKey => up(SoCParamsKey).copy( 222 L3CacheParamsOpt = None 223 ) 224 }) 225) 226 227class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 228 case XSTileKey => 229 val sets = n * 1024 / ways / 64 230 up(XSTileKey).map(_.copy( 231 dcacheParametersOpt = Some(DCacheParameters( 232 nSets = sets, 233 nWays = ways, 234 tagECC = Some("secded"), 235 dataECC = Some("secded"), 236 replacer = Some("setplru"), 237 nMissEntries = 16, 238 nProbeEntries = 8, 239 nReleaseEntries = 18 240 )) 241 )) 242}) 243 244class WithNKBL2 245( 246 n: Int, 247 ways: Int = 8, 248 inclusive: Boolean = true, 249 banks: Int = 1 250) extends Config((site, here, up) => { 251 case XSTileKey => 252 val upParams = up(XSTileKey) 253 val l2sets = n * 1024 / banks / ways / 64 254 upParams.map(p => p.copy( 255 L2CacheParamsOpt = Some(L2Param( 256 name = "L2", 257 ways = ways, 258 sets = l2sets, 259 clientCaches = Seq(L1Param( 260 "dcache", 261 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 262 ways = p.dcacheParametersOpt.get.nWays + 2, 263 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 264 )), 265 reqField = Seq(utility.ReqSourceField()), 266 echoField = Seq(huancun.DirtyField()), 267 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 268 )), 269 L2NBanks = banks 270 )) 271}) 272 273class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 274 case SoCParamsKey => 275 val sets = n * 1024 / banks / ways / 64 276 val tiles = site(XSTileKey) 277 val clientDirBytes = tiles.map{ t => 278 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 279 }.sum 280 up(SoCParamsKey).copy( 281 L3NBanks = banks, 282 L3CacheParamsOpt = Some(HCCacheParameters( 283 name = "L3", 284 level = 3, 285 ways = ways, 286 sets = sets, 287 inclusive = inclusive, 288 clientCaches = tiles.map{ core => 289 val l2params = core.L2CacheParamsOpt.get.toCacheParams 290 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 291 }, 292 enablePerf = true, 293 ctrl = Some(CacheCtrl( 294 address = 0x39000000, 295 numCores = tiles.size 296 )), 297 reqField = Seq(utility.ReqSourceField()), 298 sramClkDivBy2 = true, 299 sramDepthDiv = 4, 300 tagECC = Some("secded"), 301 dataECC = Some("secded"), 302 simulation = !site(DebugOptionsKey).FPGAPlatform 303 )) 304 ) 305}) 306 307class WithL3DebugConfig extends Config( 308 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 309) 310 311class MinimalL3DebugConfig(n: Int = 1) extends Config( 312 new WithL3DebugConfig ++ new MinimalConfig(n) 313) 314 315class DefaultL3DebugConfig(n: Int = 1) extends Config( 316 new WithL3DebugConfig ++ new BaseConfig(n) 317) 318 319class MinimalAliasDebugConfig(n: Int = 1) extends Config( 320 new WithNKBL3(512, inclusive = false) ++ 321 new WithNKBL2(256, inclusive = false) ++ 322 new WithNKBL1D(128) ++ 323 new MinimalConfig(n) 324) 325 326class MediumConfig(n: Int = 1) extends Config( 327 new WithNKBL3(4096, inclusive = false, banks = 4) 328 ++ new WithNKBL2(512, inclusive = false) 329 ++ new WithNKBL1D(128) 330 ++ new BaseConfig(n) 331) 332 333class DefaultConfig(n: Int = 1) extends Config( 334 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 335 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4) 336 ++ new WithNKBL1D(128) 337 ++ new BaseConfig(n) 338) 339