1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import xiangshan.frontend.ICacheParameters 27import freechips.rocketchip.devices.debug._ 28import freechips.rocketchip.tile.MaxHartIdBits 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.backend.exu.ExuParameters 31import xiangshan.cache.DCacheParameters 32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 33import device.{EnableJtag, XSDebugModuleParams} 34import huancun._ 35 36class BaseConfig(n: Int) extends Config((site, here, up) => { 37 case XLen => 64 38 case DebugOptionsKey => DebugOptions() 39 case SoCParamsKey => SoCParameters( 40 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 41 ) 42 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 43 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 44 case JtagDTMKey => JtagDTMKey 45 case MaxHartIdBits => 2 46 case EnableJtag => false.B 47}) 48 49// Synthesizable minimal XiangShan 50// * It is still an out-of-order, super-scalaer arch 51// * L1 cache included 52// * L2 cache NOT included 53// * L3 cache included 54class MinimalConfig(n: Int = 1) extends Config( 55 new BaseConfig(n).alter((site, here, up) => { 56 case SoCParamsKey => up(SoCParamsKey).copy( 57 cores = up(SoCParamsKey).cores.map(_.copy( 58 DecodeWidth = 2, 59 RenameWidth = 2, 60 FetchWidth = 4, 61 IssQueSize = 8, 62 NRPhyRegs = 64, 63 LoadQueueSize = 16, 64 StoreQueueSize = 12, 65 RobSize = 32, 66 FtqSize = 8, 67 IBufSize = 16, 68 StoreBufferSize = 4, 69 StoreBufferThreshold = 3, 70 dpParams = DispatchParameters( 71 IntDqSize = 12, 72 FpDqSize = 12, 73 LsDqSize = 12, 74 IntDqDeqWidth = 4, 75 FpDqDeqWidth = 4, 76 LsDqDeqWidth = 4 77 ), 78 exuParameters = ExuParameters( 79 JmpCnt = 1, 80 AluCnt = 2, 81 MulCnt = 0, 82 MduCnt = 1, 83 FmacCnt = 1, 84 FmiscCnt = 1, 85 FmiscDivSqrtCnt = 0, 86 LduCnt = 2, 87 StuCnt = 2 88 ), 89 icacheParameters = ICacheParameters( 90 nSets = 64, // 16KB ICache 91 tagECC = Some("parity"), 92 dataECC = Some("parity"), 93 replacer = Some("setplru"), 94 nMissEntries = 2 95 ), 96 dcacheParametersOpt = Some(DCacheParameters( 97 nSets = 64, // 32KB DCache 98 nWays = 8, 99 tagECC = Some("secded"), 100 dataECC = Some("secded"), 101 replacer = Some("setplru"), 102 nMissEntries = 4, 103 nProbeEntries = 4, 104 nReleaseEntries = 4, 105 nStoreReplayEntries = 4, 106 )), 107 EnableBPD = false, // disable TAGE 108 EnableLoop = false, 109 itlbParameters = TLBParameters( 110 name = "itlb", 111 fetchi = true, 112 useDmode = false, 113 sameCycle = true, 114 normalReplacer = Some("plru"), 115 superReplacer = Some("plru"), 116 normalNWays = 4, 117 normalNSets = 1, 118 superNWays = 2, 119 shouldBlock = true 120 ), 121 ldtlbParameters = TLBParameters( 122 name = "ldtlb", 123 normalNSets = 4, // when da or sa 124 normalNWays = 1, // when fa or sa 125 normalAssociative = "sa", 126 normalReplacer = Some("setplru"), 127 superNWays = 4, 128 normalAsVictim = true, 129 outReplace = true 130 ), 131 sttlbParameters = TLBParameters( 132 name = "sttlb", 133 normalNSets = 4, // when da or sa 134 normalNWays = 1, // when fa or sa 135 normalAssociative = "sa", 136 normalReplacer = Some("setplru"), 137 normalAsVictim = true, 138 superNWays = 4, 139 outReplace = true 140 ), 141 btlbParameters = TLBParameters( 142 name = "btlb", 143 normalNSets = 1, 144 normalNWays = 8, 145 superNWays = 2 146 ), 147 l2tlbParameters = L2TLBParameters( 148 l1Size = 4, 149 l2nSets = 4, 150 l2nWays = 4, 151 l3nSets = 4, 152 l3nWays = 8, 153 spSize = 2, 154 ), 155 L2CacheParamsOpt = None // remove L2 Cache 156 )), 157 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 158 sets = 1024 159 )), 160 L3NBanks = 1 161 ) 162 }) 163) 164 165// Non-synthesizable MinimalConfig, for fast simulation only 166class MinimalSimConfig(n: Int = 1) extends Config( 167 new MinimalConfig(n).alter((site, here, up) => { 168 case SoCParamsKey => up(SoCParamsKey).copy( 169 cores = up(SoCParamsKey).cores.map(_.copy( 170 dcacheParametersOpt = None, 171 softPTW = true 172 )), 173 L3CacheParamsOpt = None 174 ) 175 }) 176) 177 178class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 179 case SoCParamsKey => 180 val upParams = up(SoCParamsKey) 181 val sets = n * 1024 / ways / 64 182 upParams.copy(cores = upParams.cores.map(p => p.copy( 183 dcacheParametersOpt = Some(DCacheParameters( 184 nSets = sets, 185 nWays = ways, 186 tagECC = Some("secded"), 187 dataECC = Some("secded"), 188 replacer = Some("setplru"), 189 nMissEntries = 16, 190 nProbeEntries = 16, 191 nReleaseEntries = 16, 192 nStoreReplayEntries = 16 193 )) 194 ))) 195}) 196 197class WithNKBL2 198( 199 n: Int, 200 ways: Int = 8, 201 inclusive: Boolean = true, 202 banks: Int = 1, 203 alwaysReleaseData: Boolean = false 204) extends Config((site, here, up) => { 205 case SoCParamsKey => 206 val upParams = up(SoCParamsKey) 207 val l2sets = n * 1024 / banks / ways / 64 208 upParams.copy( 209 cores = upParams.cores.map(p => p.copy( 210 L2CacheParamsOpt = Some(HCCacheParameters( 211 name = "L2", 212 level = 2, 213 ways = ways, 214 sets = l2sets, 215 inclusive = inclusive, 216 alwaysReleaseData = alwaysReleaseData, 217 clientCaches = Seq(CacheParameters( 218 "dcache", 219 sets = 2 * p.dcacheParametersOpt.get.nSets, 220 ways = p.dcacheParametersOpt.get.nWays + 2, 221 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 222 )), 223 reqField = Seq(PreferCacheField()), 224 echoField = Seq(DirtyField()), 225 prefetch = Some(huancun.prefetch.BOPParameters()), 226 enablePerf = true 227 ) 228 ), L2NBanks = banks 229 )) 230 ) 231}) 232 233class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 234 case SoCParamsKey => 235 val upParams = up(SoCParamsKey) 236 val sets = n * 1024 / banks / ways / 64 237 upParams.copy( 238 L3NBanks = banks, 239 L3CacheParamsOpt = Some(HCCacheParameters( 240 name = "L3", 241 level = 3, 242 ways = ways, 243 sets = sets, 244 inclusive = inclusive, 245 clientCaches = upParams.cores.map{ core => 246 val l2params = core.L2CacheParamsOpt.get.toCacheParams 247 l2params.copy(sets = 2 * l2params.sets, ways = l2params.ways) 248 }, 249 enablePerf = true 250 )) 251 ) 252}) 253 254class WithL3DebugConfig extends Config( 255 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 256) 257 258class MinimalL3DebugConfig(n: Int = 1) extends Config( 259 new WithL3DebugConfig ++ new MinimalConfig(n) 260) 261 262class DefaultL3DebugConfig(n: Int = 1) extends Config( 263 new WithL3DebugConfig ++ new BaseConfig(n) 264) 265 266class MinimalAliasDebugConfig(n: Int = 1) extends Config( 267 new WithNKBL3(512, inclusive = false) ++ 268 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 269 new WithNKBL1D(128) ++ 270 new MinimalConfig(n) 271) 272 273class DefaultConfig(n: Int = 1) extends Config( 274 new WithNKBL3(4096, inclusive = false, banks = 4) 275 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 276 ++ new WithNKBL1D(128) 277 ++ new BaseConfig(n) 278) 279 280class LargeConfig(n: Int = 1) extends Config( 281 new WithNKBL3(10 * 1024, inclusive = false, banks = 4, ways = 10) 282 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 2, alwaysReleaseData = true) 283 ++ new WithNKBL1D(128) 284 ++ new BaseConfig(n) 285)