1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import chipsalliance.rocketchip.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.MaxHartIdBits 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.exu.ExuParameters 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36 37class BaseConfig(n: Int) extends Config((site, here, up) => { 38 case XLen => 64 39 case DebugOptionsKey => DebugOptions() 40 case SoCParamsKey => SoCParameters() 41 case PMParameKey => PMParameters() 42 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 43 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 44 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 45 case JtagDTMKey => JtagDTMKey 46 case MaxHartIdBits => 2 47 case EnableJtag => true.B 48}) 49 50// Synthesizable minimal XiangShan 51// * It is still an out-of-order, super-scalaer arch 52// * L1 cache included 53// * L2 cache NOT included 54// * L3 cache included 55class MinimalConfig(n: Int = 1) extends Config( 56 new BaseConfig(n).alter((site, here, up) => { 57 case XSTileKey => up(XSTileKey).map( 58 _.copy( 59 DecodeWidth = 2, 60 RenameWidth = 2, 61 CommitWidth = 2, 62 FetchWidth = 4, 63 IssQueSize = 8, 64 NRPhyRegs = 64, 65 LoadQueueSize = 16, 66 LoadQueueNWriteBanks = 4, 67 StoreQueueSize = 12, 68 StoreQueueNWriteBanks = 4, 69 RobSize = 32, 70 FtqSize = 8, 71 IBufSize = 16, 72 StoreBufferSize = 4, 73 StoreBufferThreshold = 3, 74 dpParams = DispatchParameters( 75 IntDqSize = 12, 76 FpDqSize = 12, 77 LsDqSize = 12, 78 IntDqDeqWidth = 4, 79 FpDqDeqWidth = 4, 80 LsDqDeqWidth = 4 81 ), 82 exuParameters = ExuParameters( 83 JmpCnt = 1, 84 AluCnt = 2, 85 MulCnt = 0, 86 MduCnt = 1, 87 FmacCnt = 1, 88 FmiscCnt = 1, 89 FmiscDivSqrtCnt = 0, 90 LduCnt = 2, 91 StuCnt = 2 92 ), 93 icacheParameters = ICacheParameters( 94 nSets = 64, // 16KB ICache 95 tagECC = Some("parity"), 96 dataECC = Some("parity"), 97 replacer = Some("setplru"), 98 nMissEntries = 2, 99 nReleaseEntries = 1, 100 nProbeEntries = 2, 101 nPrefetchEntries = 2, 102 nPrefBufferEntries = 32, 103 hasPrefetch = true 104 ), 105 dcacheParametersOpt = Some(DCacheParameters( 106 nSets = 64, // 32KB DCache 107 nWays = 8, 108 tagECC = Some("secded"), 109 dataECC = Some("secded"), 110 replacer = Some("setplru"), 111 nMissEntries = 4, 112 nProbeEntries = 4, 113 nReleaseEntries = 8, 114 )), 115 EnableBPD = false, // disable TAGE 116 EnableLoop = false, 117 itlbParameters = TLBParameters( 118 name = "itlb", 119 fetchi = true, 120 useDmode = false, 121 normalReplacer = Some("plru"), 122 superReplacer = Some("plru"), 123 normalNWays = 4, 124 normalNSets = 1, 125 superNWays = 2 126 ), 127 ldtlbParameters = TLBParameters( 128 name = "ldtlb", 129 normalNSets = 16, // when da or sa 130 normalNWays = 1, // when fa or sa 131 normalAssociative = "sa", 132 normalReplacer = Some("setplru"), 133 superNWays = 4, 134 normalAsVictim = true, 135 partialStaticPMP = true, 136 outsideRecvFlush = true, 137 outReplace = false 138 ), 139 sttlbParameters = TLBParameters( 140 name = "sttlb", 141 normalNSets = 16, // when da or sa 142 normalNWays = 1, // when fa or sa 143 normalAssociative = "sa", 144 normalReplacer = Some("setplru"), 145 normalAsVictim = true, 146 superNWays = 4, 147 partialStaticPMP = true, 148 outsideRecvFlush = true, 149 outReplace = false 150 ), 151 btlbParameters = TLBParameters( 152 name = "btlb", 153 normalNSets = 1, 154 normalNWays = 8, 155 superNWays = 2 156 ), 157 l2tlbParameters = L2TLBParameters( 158 l1Size = 4, 159 l2nSets = 4, 160 l2nWays = 4, 161 l3nSets = 4, 162 l3nWays = 8, 163 spSize = 2, 164 ), 165 L2CacheParamsOpt = None, // remove L2 Cache 166 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 167 ) 168 ) 169 case SoCParamsKey => 170 val tiles = site(XSTileKey) 171 up(SoCParamsKey).copy( 172 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 173 sets = 1024, 174 inclusive = false, 175 clientCaches = tiles.map{ p => 176 CacheParameters( 177 "dcache", 178 sets = 2 * p.dcacheParametersOpt.get.nSets, 179 ways = p.dcacheParametersOpt.get.nWays + 2, 180 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets), 181 aliasBitsOpt = None 182 ) 183 }, 184 simulation = !site(DebugOptionsKey).FPGAPlatform 185 )), 186 L3NBanks = 1 187 ) 188 }) 189) 190 191// Non-synthesizable MinimalConfig, for fast simulation only 192class MinimalSimConfig(n: Int = 1) extends Config( 193 new MinimalConfig(n).alter((site, here, up) => { 194 case XSTileKey => up(XSTileKey).map(_.copy( 195 dcacheParametersOpt = None, 196 softPTW = true 197 )) 198 case SoCParamsKey => up(SoCParamsKey).copy( 199 L3CacheParamsOpt = None 200 ) 201 }) 202) 203 204class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 205 case XSTileKey => 206 val sets = n * 1024 / ways / 64 207 up(XSTileKey).map(_.copy( 208 dcacheParametersOpt = Some(DCacheParameters( 209 nSets = sets, 210 nWays = ways, 211 tagECC = Some("secded"), 212 dataECC = Some("secded"), 213 replacer = Some("setplru"), 214 nMissEntries = 16, 215 nProbeEntries = 8, 216 nReleaseEntries = 18 217 )) 218 )) 219}) 220 221class WithNKBL2 222( 223 n: Int, 224 ways: Int = 8, 225 inclusive: Boolean = true, 226 banks: Int = 1, 227 alwaysReleaseData: Boolean = false 228) extends Config((site, here, up) => { 229 case XSTileKey => 230 val upParams = up(XSTileKey) 231 val l2sets = n * 1024 / banks / ways / 64 232 upParams.map(p => p.copy( 233 L2CacheParamsOpt = Some(HCCacheParameters( 234 name = "L2", 235 level = 2, 236 ways = ways, 237 sets = l2sets, 238 inclusive = inclusive, 239 alwaysReleaseData = alwaysReleaseData, 240 clientCaches = Seq(CacheParameters( 241 "dcache", 242 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 243 ways = p.dcacheParametersOpt.get.nWays + 2, 244 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets / banks), 245 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 246 )), 247 reqField = Seq(PreferCacheField()), 248 echoField = Seq(DirtyField()), 249 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()), 250 enablePerf = true, 251 sramDepthDiv = 2, 252 tagECC = Some("secded"), 253 dataECC = Some("secded"), 254 simulation = !site(DebugOptionsKey).FPGAPlatform 255 )), 256 L2NBanks = banks 257 )) 258}) 259 260class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 261 case SoCParamsKey => 262 val sets = n * 1024 / banks / ways / 64 263 val tiles = site(XSTileKey) 264 val clientDirBytes = tiles.map{ t => 265 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 266 }.sum 267 up(SoCParamsKey).copy( 268 L3NBanks = banks, 269 L3CacheParamsOpt = Some(HCCacheParameters( 270 name = "L3", 271 level = 3, 272 ways = ways, 273 sets = sets, 274 inclusive = inclusive, 275 clientCaches = tiles.map{ core => 276 val l2params = core.L2CacheParamsOpt.get.toCacheParams 277 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 278 }, 279 enablePerf = true, 280 ctrl = Some(CacheCtrl( 281 address = 0x39000000, 282 numCores = tiles.size 283 )), 284 sramClkDivBy2 = true, 285 sramDepthDiv = 4, 286 tagECC = Some("secded"), 287 dataECC = Some("secded"), 288 simulation = !site(DebugOptionsKey).FPGAPlatform 289 )) 290 ) 291}) 292 293class WithL3DebugConfig extends Config( 294 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 295) 296 297class MinimalL3DebugConfig(n: Int = 1) extends Config( 298 new WithL3DebugConfig ++ new MinimalConfig(n) 299) 300 301class DefaultL3DebugConfig(n: Int = 1) extends Config( 302 new WithL3DebugConfig ++ new BaseConfig(n) 303) 304 305class MinimalAliasDebugConfig(n: Int = 1) extends Config( 306 new WithNKBL3(512, inclusive = false) ++ 307 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 308 new WithNKBL1D(128) ++ 309 new MinimalConfig(n) 310) 311 312class MediumConfig(n: Int = 1) extends Config( 313 new WithNKBL3(4096, inclusive = false, banks = 4) 314 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 315 ++ new WithNKBL1D(128) 316 ++ new BaseConfig(n) 317) 318 319class DefaultConfig(n: Int = 1) extends Config( 320 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 321 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 322 ++ new WithNKBL1D(128) 323 ++ new BaseConfig(n) 324) 325