1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import xiangshan.frontend.icache.ICacheParameters 43 44class BaseConfig(n: Int) extends Config((site, here, up) => { 45 case XLen => 64 46 case DebugOptionsKey => DebugOptions() 47 case SoCParamsKey => SoCParameters() 48 case PMParameKey => PMParameters() 49 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 50 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 51 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 52 case JtagDTMKey => JtagDTMKey 53 case MaxHartIdBits => log2Up(n) 54 case EnableJtag => true.B 55}) 56 57// Synthesizable minimal XiangShan 58// * It is still an out-of-order, super-scalaer arch 59// * L1 cache included 60// * L2 cache NOT included 61// * L3 cache included 62class MinimalConfig(n: Int = 1) extends Config( 63 new BaseConfig(n).alter((site, here, up) => { 64 case XSTileKey => up(XSTileKey).map( 65 p => p.copy( 66 DecodeWidth = 6, 67 RenameWidth = 6, 68 RobCommitWidth = 8, 69 FetchWidth = 4, 70 VirtualLoadQueueSize = 24, 71 LoadQueueRARSize = 24, 72 LoadQueueRAWSize = 12, 73 LoadQueueReplaySize = 24, 74 LoadUncacheBufferSize = 8, 75 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 76 RollbackGroupSize = 8, 77 StoreQueueSize = 20, 78 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 79 StoreQueueForwardWithMask = true, 80 // ============ VLSU ============ 81 VlMergeBufferSize = 8, 82 VsMergeBufferSize = 8, 83 UopWritebackWidth = 1, 84 SplitBufferSize = 8, 85 // ============================== 86 RobSize = 48, 87 RabSize = 96, 88 FtqSize = 8, 89 IBufSize = 24, 90 IBufNBank = 6, 91 StoreBufferSize = 4, 92 StoreBufferThreshold = 3, 93 IssueQueueSize = 8, 94 IssueQueueCompEntrySize = 4, 95 dpParams = DispatchParameters( 96 IntDqSize = 12, 97 FpDqSize = 12, 98 LsDqSize = 12, 99 IntDqDeqWidth = 8, 100 FpDqDeqWidth = 6, 101 VecDqDeqWidth = 6, 102 LsDqDeqWidth = 6 103 ), 104 intPreg = IntPregParams( 105 numEntries = 64, 106 numRead = None, 107 numWrite = None, 108 ), 109 vfPreg = VfPregParams( 110 numEntries = 160, 111 numRead = None, 112 numWrite = None, 113 ), 114 icacheParameters = ICacheParameters( 115 nSets = 64, // 16KB ICache 116 tagECC = Some("parity"), 117 dataECC = Some("parity"), 118 replacer = Some("setplru"), 119 nMissEntries = 2, 120 nReleaseEntries = 1, 121 nProbeEntries = 2, 122 // fdip 123 enableICachePrefetch = true, 124 prefetchToL1 = false, 125 ), 126 dcacheParametersOpt = Some(DCacheParameters( 127 nSets = 64, // 32KB DCache 128 nWays = 8, 129 tagECC = Some("secded"), 130 dataECC = Some("secded"), 131 replacer = Some("setplru"), 132 nMissEntries = 4, 133 nProbeEntries = 4, 134 nReleaseEntries = 8, 135 nMaxPrefetchEntry = 2, 136 )), 137 EnableBPD = false, // disable TAGE 138 EnableLoop = false, 139 itlbParameters = TLBParameters( 140 name = "itlb", 141 fetchi = true, 142 useDmode = false, 143 NWays = 4, 144 ), 145 ldtlbParameters = TLBParameters( 146 name = "ldtlb", 147 NWays = 4, 148 partialStaticPMP = true, 149 outsideRecvFlush = true, 150 outReplace = false, 151 lgMaxSize = 4 152 ), 153 sttlbParameters = TLBParameters( 154 name = "sttlb", 155 NWays = 4, 156 partialStaticPMP = true, 157 outsideRecvFlush = true, 158 outReplace = false, 159 lgMaxSize = 4 160 ), 161 hytlbParameters = TLBParameters( 162 name = "hytlb", 163 NWays = 4, 164 partialStaticPMP = true, 165 outsideRecvFlush = true, 166 outReplace = false, 167 lgMaxSize = 4 168 ), 169 pftlbParameters = TLBParameters( 170 name = "pftlb", 171 NWays = 4, 172 partialStaticPMP = true, 173 outsideRecvFlush = true, 174 outReplace = false, 175 lgMaxSize = 4 176 ), 177 btlbParameters = TLBParameters( 178 name = "btlb", 179 NWays = 4, 180 ), 181 l2tlbParameters = L2TLBParameters( 182 l1Size = 4, 183 l2nSets = 4, 184 l2nWays = 4, 185 l3nSets = 4, 186 l3nWays = 8, 187 spSize = 2, 188 ), 189 L2CacheParamsOpt = Some(L2Param( 190 name = "L2", 191 ways = 8, 192 sets = 128, 193 echoField = Seq(huancun.DirtyField()), 194 prefetch = None, 195 clientCaches = Seq(L1Param( 196 "dcache", 197 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 198 )), 199 ) 200 ), 201 L2NBanks = 2, 202 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 203 ) 204 ) 205 case SoCParamsKey => 206 val tiles = site(XSTileKey) 207 up(SoCParamsKey).copy( 208 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 209 sets = 1024, 210 inclusive = false, 211 clientCaches = tiles.map{ core => 212 val clientDirBytes = tiles.map{ t => 213 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 214 }.sum 215 val l2params = core.L2CacheParamsOpt.get.toCacheParams 216 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 217 }, 218 simulation = !site(DebugOptionsKey).FPGAPlatform, 219 prefetch = None 220 )), 221 L3NBanks = 1 222 ) 223 }) 224) 225 226// Non-synthesizable MinimalConfig, for fast simulation only 227class MinimalSimConfig(n: Int = 1) extends Config( 228 new MinimalConfig(n).alter((site, here, up) => { 229 case XSTileKey => up(XSTileKey).map(_.copy( 230 dcacheParametersOpt = None, 231 softPTW = true 232 )) 233 case SoCParamsKey => up(SoCParamsKey).copy( 234 L3CacheParamsOpt = None 235 ) 236 }) 237) 238 239class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 240 case XSTileKey => 241 val sets = n * 1024 / ways / 64 242 up(XSTileKey).map(_.copy( 243 dcacheParametersOpt = Some(DCacheParameters( 244 nSets = sets, 245 nWays = ways, 246 tagECC = Some("secded"), 247 dataECC = Some("secded"), 248 replacer = Some("setplru"), 249 nMissEntries = 16, 250 nProbeEntries = 8, 251 nReleaseEntries = 18, 252 nMaxPrefetchEntry = 6, 253 )) 254 )) 255}) 256 257class WithNKBL2 258( 259 n: Int, 260 ways: Int = 8, 261 inclusive: Boolean = true, 262 banks: Int = 1 263) extends Config((site, here, up) => { 264 case XSTileKey => 265 require(inclusive, "L2 must be inclusive") 266 val upParams = up(XSTileKey) 267 val l2sets = n * 1024 / banks / ways / 64 268 upParams.map(p => p.copy( 269 L2CacheParamsOpt = Some(L2Param( 270 name = "L2", 271 ways = ways, 272 sets = l2sets, 273 clientCaches = Seq(L1Param( 274 "dcache", 275 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 276 ways = p.dcacheParametersOpt.get.nWays + 2, 277 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 278 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)), 279 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 280 )), 281 reqField = Seq(utility.ReqSourceField()), 282 echoField = Seq(huancun.DirtyField()), 283 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()), 284 enablePerf = !site(DebugOptionsKey).FPGAPlatform, 285 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 286 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 287 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 288 )), 289 L2NBanks = banks 290 )) 291}) 292 293class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 294 case SoCParamsKey => 295 val sets = n * 1024 / banks / ways / 64 296 val tiles = site(XSTileKey) 297 val clientDirBytes = tiles.map{ t => 298 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 299 }.sum 300 up(SoCParamsKey).copy( 301 L3NBanks = banks, 302 L3CacheParamsOpt = Some(HCCacheParameters( 303 name = "L3", 304 level = 3, 305 ways = ways, 306 sets = sets, 307 inclusive = inclusive, 308 clientCaches = tiles.map{ core => 309 val l2params = core.L2CacheParamsOpt.get.toCacheParams 310 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 311 }, 312 enablePerf = true, 313 ctrl = Some(CacheCtrl( 314 address = 0x39000000, 315 numCores = tiles.size 316 )), 317 reqField = Seq(utility.ReqSourceField()), 318 sramClkDivBy2 = true, 319 sramDepthDiv = 4, 320 tagECC = Some("secded"), 321 dataECC = Some("secded"), 322 simulation = !site(DebugOptionsKey).FPGAPlatform, 323 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 324 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 325 )) 326 ) 327}) 328 329class WithL3DebugConfig extends Config( 330 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 331) 332 333class MinimalL3DebugConfig(n: Int = 1) extends Config( 334 new WithL3DebugConfig ++ new MinimalConfig(n) 335) 336 337class DefaultL3DebugConfig(n: Int = 1) extends Config( 338 new WithL3DebugConfig ++ new BaseConfig(n) 339) 340 341class WithFuzzer extends Config((site, here, up) => { 342 case DebugOptionsKey => up(DebugOptionsKey).copy( 343 EnablePerfDebug = false, 344 ) 345 case SoCParamsKey => up(SoCParamsKey).copy( 346 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 347 enablePerf = false, 348 )), 349 ) 350 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 351 p.copy( 352 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 353 enablePerf = false, 354 )), 355 ) 356 } 357}) 358 359class MinimalAliasDebugConfig(n: Int = 1) extends Config( 360 new WithNKBL3(512, inclusive = false) ++ 361 new WithNKBL2(256, inclusive = true) ++ 362 new WithNKBL1D(128) ++ 363 new MinimalConfig(n) 364) 365 366class MediumConfig(n: Int = 1) extends Config( 367 new WithNKBL3(4096, inclusive = false, banks = 4) 368 ++ new WithNKBL2(512, inclusive = true) 369 ++ new WithNKBL1D(128) 370 ++ new BaseConfig(n) 371) 372 373class FuzzConfig(dummy: Int = 0) extends Config( 374 new WithFuzzer 375 ++ new DefaultConfig(1) 376) 377 378class DefaultConfig(n: Int = 1) extends Config( 379 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 380 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 381 ++ new WithNKBL1D(64, ways = 8) 382 ++ new BaseConfig(n) 383) 384