xref: /XiangShan/src/main/scala/top/Configs.scala (revision 98c716025d86d6220b2762171d9383f72e72cfe7) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import system._
24import chipsalliance.rocketchip.config._
25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}
26import xiangshan.frontend.icache.ICacheParameters
27import freechips.rocketchip.devices.debug._
28import freechips.rocketchip.tile.MaxHartIdBits
29import xiangshan.backend.dispatch.DispatchParameters
30import xiangshan.backend.exu.ExuParameters
31import xiangshan.cache.DCacheParameters
32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
33import device.{EnableJtag, XSDebugModuleParams}
34import huancun._
35
36class BaseConfig(n: Int) extends Config((site, here, up) => {
37  case XLen => 64
38  case DebugOptionsKey => DebugOptions()
39  case SoCParamsKey => SoCParameters()
40  case PMParameKey => PMParameters()
41  case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) }
42  case ExportDebug => DebugAttachParams(protocols = Set(JTAG))
43  case DebugModuleKey => Some(XSDebugModuleParams(site(XLen)))
44  case JtagDTMKey => JtagDTMKey
45  case MaxHartIdBits => 2
46  case EnableJtag => false.B
47})
48
49// Synthesizable minimal XiangShan
50// * It is still an out-of-order, super-scalaer arch
51// * L1 cache included
52// * L2 cache NOT included
53// * L3 cache included
54class MinimalConfig(n: Int = 1) extends Config(
55  new BaseConfig(n).alter((site, here, up) => {
56    case XSTileKey => up(XSTileKey).map(
57      _.copy(
58        DecodeWidth = 2,
59        RenameWidth = 2,
60        FetchWidth = 4,
61        IssQueSize = 8,
62        NRPhyRegs = 64,
63        LoadQueueSize = 16,
64        StoreQueueSize = 12,
65        RobSize = 32,
66        FtqSize = 8,
67        IBufSize = 16,
68        StoreBufferSize = 4,
69        StoreBufferThreshold = 3,
70        dpParams = DispatchParameters(
71          IntDqSize = 12,
72          FpDqSize = 12,
73          LsDqSize = 12,
74          IntDqDeqWidth = 4,
75          FpDqDeqWidth = 4,
76          LsDqDeqWidth = 4
77        ),
78        exuParameters = ExuParameters(
79          JmpCnt = 1,
80          AluCnt = 2,
81          MulCnt = 0,
82          MduCnt = 1,
83          FmacCnt = 1,
84          FmiscCnt = 1,
85          FmiscDivSqrtCnt = 0,
86          LduCnt = 2,
87          StuCnt = 2
88        ),
89        icacheParameters = ICacheParameters(
90          nSets = 64, // 16KB ICache
91          tagECC = Some("parity"),
92          dataECC = Some("parity"),
93          replacer = Some("setplru"),
94          nMissEntries = 2,
95          nReleaseEntries = 2
96        ),
97        dcacheParametersOpt = Some(DCacheParameters(
98          nSets = 64, // 32KB DCache
99          nWays = 8,
100          tagECC = Some("secded"),
101          dataECC = Some("secded"),
102          replacer = Some("setplru"),
103          nMissEntries = 4,
104          nProbeEntries = 4,
105          nReleaseEntries = 8,
106        )),
107        EnableBPD = false, // disable TAGE
108        EnableLoop = false,
109        itlbParameters = TLBParameters(
110          name = "itlb",
111          fetchi = true,
112          useDmode = false,
113          sameCycle = true,
114          normalReplacer = Some("plru"),
115          superReplacer = Some("plru"),
116          normalNWays = 4,
117          normalNSets = 1,
118          superNWays = 2,
119          shouldBlock = true
120        ),
121        ldtlbParameters = TLBParameters(
122          name = "ldtlb",
123          normalNSets = 4, // when da or sa
124          normalNWays = 1, // when fa or sa
125          normalAssociative = "sa",
126          normalReplacer = Some("setplru"),
127          superNWays = 4,
128          normalAsVictim = true,
129          outReplace = true
130        ),
131        sttlbParameters = TLBParameters(
132          name = "sttlb",
133          normalNSets = 4, // when da or sa
134          normalNWays = 1, // when fa or sa
135          normalAssociative = "sa",
136          normalReplacer = Some("setplru"),
137          normalAsVictim = true,
138          superNWays = 4,
139          outReplace = true
140        ),
141        btlbParameters = TLBParameters(
142          name = "btlb",
143          normalNSets = 1,
144          normalNWays = 8,
145          superNWays = 2
146        ),
147        l2tlbParameters = L2TLBParameters(
148          l1Size = 4,
149          l2nSets = 4,
150          l2nWays = 4,
151          l3nSets = 4,
152          l3nWays = 8,
153          spSize = 2,
154        ),
155        L2CacheParamsOpt = None // remove L2 Cache
156      )
157    )
158    case SoCParamsKey => up(SoCParamsKey).copy(
159      L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy(
160        sets = 1024
161      )),
162      L3NBanks = 1
163    )
164  })
165)
166
167// Non-synthesizable MinimalConfig, for fast simulation only
168class MinimalSimConfig(n: Int = 1) extends Config(
169  new MinimalConfig(n).alter((site, here, up) => {
170    case XSTileKey => up(XSTileKey).map(_.copy(
171      dcacheParametersOpt = None,
172      softPTW = true
173    ))
174    case SoCParamsKey => up(SoCParamsKey).copy(
175      L3CacheParamsOpt = None
176    )
177  })
178)
179
180class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => {
181  case XSTileKey =>
182    val sets = n * 1024 / ways / 64
183    up(XSTileKey).map(_.copy(
184      dcacheParametersOpt = Some(DCacheParameters(
185        nSets = sets,
186        nWays = ways,
187        tagECC = Some("secded"),
188        dataECC = Some("secded"),
189        replacer = Some("setplru"),
190        nMissEntries = 16,
191        nProbeEntries = 8,
192        nReleaseEntries = 18
193      ))
194    ))
195})
196
197class WithNKBL2
198(
199  n: Int,
200  ways: Int = 8,
201  inclusive: Boolean = true,
202  banks: Int = 1,
203  alwaysReleaseData: Boolean = false
204) extends Config((site, here, up) => {
205  case XSTileKey =>
206    val upParams = up(XSTileKey)
207    val l2sets = n * 1024 / banks / ways / 64
208    upParams.map(p => p.copy(
209      L2CacheParamsOpt = Some(HCCacheParameters(
210        name = "L2",
211        level = 2,
212        ways = ways,
213        sets = l2sets,
214        inclusive = inclusive,
215        alwaysReleaseData = alwaysReleaseData,
216        clientCaches = Seq(CacheParameters(
217          "dcache",
218          sets = 2 * p.dcacheParametersOpt.get.nSets,
219          ways = p.dcacheParametersOpt.get.nWays + 2,
220          aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt
221        )),
222        reqField = Seq(PreferCacheField()),
223        echoField = Seq(DirtyField()),
224        prefetch = Some(huancun.prefetch.BOPParameters()),
225        enablePerf = true
226      )),
227      L2NBanks = banks
228    ))
229})
230
231class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => {
232  case SoCParamsKey =>
233    val sets = n * 1024 / banks / ways / 64
234    val tiles = site(XSTileKey)
235    up(SoCParamsKey).copy(
236      L3NBanks = banks,
237      L3CacheParamsOpt = Some(HCCacheParameters(
238        name = "L3",
239        level = 3,
240        ways = ways,
241        sets = sets,
242        inclusive = inclusive,
243        clientCaches = tiles.map{ core =>
244          val l2params = core.L2CacheParamsOpt.get.toCacheParams
245          l2params.copy(sets = 2 * l2params.sets, ways = l2params.ways)
246        },
247        enablePerf = true,
248        ctrl = Some(CacheCtrl(
249          address = 0x39000000,
250          numCores = tiles.size
251        )),
252        sramClkDivBy2 = true
253      ))
254    )
255})
256
257class WithL3DebugConfig extends Config(
258  new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64)
259)
260
261class MinimalL3DebugConfig(n: Int = 1) extends Config(
262  new WithL3DebugConfig ++ new MinimalConfig(n)
263)
264
265class DefaultL3DebugConfig(n: Int = 1) extends Config(
266  new WithL3DebugConfig ++ new BaseConfig(n)
267)
268
269class MinimalAliasDebugConfig(n: Int = 1) extends Config(
270  new WithNKBL3(512, inclusive = false) ++
271    new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++
272    new WithNKBL1D(128) ++
273    new MinimalConfig(n)
274)
275
276class MediumConfig(n: Int = 1) extends Config(
277  new WithNKBL3(4096, inclusive = false, banks = 4)
278    ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true)
279    ++ new WithNKBL1D(128)
280    ++ new BaseConfig(n)
281)
282
283class DefaultConfig(n: Int = 1) extends Config(
284  new WithNKBL3(8 * 1024, inclusive = false, banks = 4, ways = 8)
285    ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true)
286    ++ new WithNKBL1D(128)
287    ++ new BaseConfig(n)
288)
289