1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import xiangshan.frontend.icache.ICacheParameters 43 44class BaseConfig(n: Int) extends Config((site, here, up) => { 45 case XLen => 64 46 case DebugOptionsKey => DebugOptions() 47 case SoCParamsKey => SoCParameters() 48 case PMParameKey => PMParameters() 49 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 50 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 51 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 52 case JtagDTMKey => JtagDTMKey 53 case MaxHartIdBits => 2 54 case EnableJtag => true.B 55}) 56 57// Synthesizable minimal XiangShan 58// * It is still an out-of-order, super-scalaer arch 59// * L1 cache included 60// * L2 cache NOT included 61// * L3 cache included 62class MinimalConfig(n: Int = 1) extends Config( 63 new BaseConfig(n).alter((site, here, up) => { 64 case XSTileKey => up(XSTileKey).map( 65 _.copy( 66 DecodeWidth = 2, 67 RenameWidth = 2, 68 CommitWidth = 2, 69 FetchWidth = 4, 70 VirtualLoadQueueSize = 24, 71 LoadQueueRARSize = 16, 72 LoadQueueRAWSize = 12, 73 LoadQueueReplaySize = 24, 74 LoadUncacheBufferSize = 8, 75 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 76 RollbackGroupSize = 8, 77 StoreQueueSize = 20, 78 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 79 StoreQueueForwardWithMask = true, 80 RobSize = 48, 81 RabSize = 96, 82 FtqSize = 8, 83 IBufSize = 16, 84 IBufNBank = 2, 85 StoreBufferSize = 4, 86 StoreBufferThreshold = 3, 87 IssueQueueSize = 8, 88 IssueQueueCompEntrySize = 4, 89 dpParams = DispatchParameters( 90 IntDqSize = 12, 91 FpDqSize = 12, 92 LsDqSize = 12, 93 IntDqDeqWidth = 8, 94 FpDqDeqWidth = 4, 95 LsDqDeqWidth = 6 96 ), 97 intPreg = IntPregParams( 98 numEntries = 64, 99 numRead = None, 100 numWrite = None, 101 ), 102 vfPreg = VfPregParams( 103 numEntries = 160, 104 numRead = Some(14), 105 numWrite = None, 106 ), 107 icacheParameters = ICacheParameters( 108 nSets = 64, // 16KB ICache 109 tagECC = Some("parity"), 110 dataECC = Some("parity"), 111 replacer = Some("setplru"), 112 nMissEntries = 2, 113 nReleaseEntries = 1, 114 nProbeEntries = 2, 115 // fdip 116 enableICachePrefetch = true, 117 prefetchToL1 = false, 118 ), 119 dcacheParametersOpt = Some(DCacheParameters( 120 nSets = 64, // 32KB DCache 121 nWays = 8, 122 tagECC = Some("secded"), 123 dataECC = Some("secded"), 124 replacer = Some("setplru"), 125 nMissEntries = 4, 126 nProbeEntries = 4, 127 nReleaseEntries = 8, 128 nMaxPrefetchEntry = 2, 129 )), 130 EnableBPD = false, // disable TAGE 131 EnableLoop = false, 132 itlbParameters = TLBParameters( 133 name = "itlb", 134 fetchi = true, 135 useDmode = false, 136 NWays = 4, 137 ), 138 ldtlbParameters = TLBParameters( 139 name = "ldtlb", 140 NWays = 4, 141 partialStaticPMP = true, 142 outsideRecvFlush = true, 143 outReplace = false 144 ), 145 sttlbParameters = TLBParameters( 146 name = "sttlb", 147 NWays = 4, 148 partialStaticPMP = true, 149 outsideRecvFlush = true, 150 outReplace = false 151 ), 152 hytlbParameters = TLBParameters( 153 name = "hytlb", 154 NWays = 4, 155 partialStaticPMP = true, 156 outsideRecvFlush = true, 157 outReplace = false 158 ), 159 pftlbParameters = TLBParameters( 160 name = "pftlb", 161 NWays = 4, 162 partialStaticPMP = true, 163 outsideRecvFlush = true, 164 outReplace = false 165 ), 166 btlbParameters = TLBParameters( 167 name = "btlb", 168 NWays = 4, 169 ), 170 l2tlbParameters = L2TLBParameters( 171 l1Size = 4, 172 l2nSets = 4, 173 l2nWays = 4, 174 l3nSets = 4, 175 l3nWays = 8, 176 spSize = 2, 177 ), 178 L2CacheParamsOpt = Some(L2Param( 179 name = "L2", 180 ways = 8, 181 sets = 128, 182 echoField = Seq(huancun.DirtyField()), 183 prefetch = None 184 )), 185 L2NBanks = 2, 186 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 187 ) 188 ) 189 case SoCParamsKey => 190 val tiles = site(XSTileKey) 191 up(SoCParamsKey).copy( 192 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 193 sets = 1024, 194 inclusive = false, 195 clientCaches = tiles.map{ core => 196 val clientDirBytes = tiles.map{ t => 197 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 198 }.sum 199 val l2params = core.L2CacheParamsOpt.get.toCacheParams 200 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 201 }, 202 simulation = !site(DebugOptionsKey).FPGAPlatform, 203 prefetch = None 204 )), 205 L3NBanks = 1 206 ) 207 }) 208) 209 210// Non-synthesizable MinimalConfig, for fast simulation only 211class MinimalSimConfig(n: Int = 1) extends Config( 212 new MinimalConfig(n).alter((site, here, up) => { 213 case XSTileKey => up(XSTileKey).map(_.copy( 214 dcacheParametersOpt = None, 215 softPTW = true 216 )) 217 case SoCParamsKey => up(SoCParamsKey).copy( 218 L3CacheParamsOpt = None 219 ) 220 }) 221) 222 223class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 224 case XSTileKey => 225 val sets = n * 1024 / ways / 64 226 up(XSTileKey).map(_.copy( 227 dcacheParametersOpt = Some(DCacheParameters( 228 nSets = sets, 229 nWays = ways, 230 tagECC = Some("secded"), 231 dataECC = Some("secded"), 232 replacer = Some("setplru"), 233 nMissEntries = 16, 234 nProbeEntries = 8, 235 nReleaseEntries = 18, 236 nMaxPrefetchEntry = 6, 237 )) 238 )) 239}) 240 241class WithNKBL2 242( 243 n: Int, 244 ways: Int = 8, 245 inclusive: Boolean = true, 246 banks: Int = 1 247) extends Config((site, here, up) => { 248 case XSTileKey => 249 require(inclusive, "L2 must be inclusive") 250 val upParams = up(XSTileKey) 251 val l2sets = n * 1024 / banks / ways / 64 252 upParams.map(p => p.copy( 253 L2CacheParamsOpt = Some(L2Param( 254 name = "L2", 255 ways = ways, 256 sets = l2sets, 257 clientCaches = Seq(L1Param( 258 "dcache", 259 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 260 ways = p.dcacheParametersOpt.get.nWays + 2, 261 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 262 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)) 263 )), 264 reqField = Seq(utility.ReqSourceField()), 265 echoField = Seq(huancun.DirtyField()), 266 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()), 267 enablePerf = !site(DebugOptionsKey).FPGAPlatform, 268 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 269 )), 270 L2NBanks = banks 271 )) 272}) 273 274class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 275 case SoCParamsKey => 276 val sets = n * 1024 / banks / ways / 64 277 val tiles = site(XSTileKey) 278 val clientDirBytes = tiles.map{ t => 279 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 280 }.sum 281 up(SoCParamsKey).copy( 282 L3NBanks = banks, 283 L3CacheParamsOpt = Some(HCCacheParameters( 284 name = "L3", 285 level = 3, 286 ways = ways, 287 sets = sets, 288 inclusive = inclusive, 289 clientCaches = tiles.map{ core => 290 val l2params = core.L2CacheParamsOpt.get.toCacheParams 291 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 292 }, 293 enablePerf = true, 294 ctrl = Some(CacheCtrl( 295 address = 0x39000000, 296 numCores = tiles.size 297 )), 298 reqField = Seq(utility.ReqSourceField()), 299 sramClkDivBy2 = true, 300 sramDepthDiv = 4, 301 tagECC = Some("secded"), 302 dataECC = Some("secded"), 303 simulation = !site(DebugOptionsKey).FPGAPlatform, 304 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 305 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 306 )) 307 ) 308}) 309 310class WithL3DebugConfig extends Config( 311 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 312) 313 314class MinimalL3DebugConfig(n: Int = 1) extends Config( 315 new WithL3DebugConfig ++ new MinimalConfig(n) 316) 317 318class DefaultL3DebugConfig(n: Int = 1) extends Config( 319 new WithL3DebugConfig ++ new BaseConfig(n) 320) 321 322class WithFuzzer extends Config((site, here, up) => { 323 case DebugOptionsKey => up(DebugOptionsKey).copy( 324 EnablePerfDebug = false, 325 ) 326 case SoCParamsKey => up(SoCParamsKey).copy( 327 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 328 enablePerf = false, 329 )), 330 ) 331 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 332 p.copy( 333 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 334 enablePerf = false, 335 )), 336 ) 337 } 338}) 339 340class MinimalAliasDebugConfig(n: Int = 1) extends Config( 341 new WithNKBL3(512, inclusive = false) ++ 342 new WithNKBL2(256, inclusive = true) ++ 343 new WithNKBL1D(128) ++ 344 new MinimalConfig(n) 345) 346 347class MediumConfig(n: Int = 1) extends Config( 348 new WithNKBL3(4096, inclusive = false, banks = 4) 349 ++ new WithNKBL2(512, inclusive = true) 350 ++ new WithNKBL1D(128) 351 ++ new BaseConfig(n) 352) 353 354class FuzzConfig(dummy: Int = 0) extends Config( 355 new WithFuzzer 356 ++ new DefaultConfig(1) 357) 358 359class DefaultConfig(n: Int = 1) extends Config( 360 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 361 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 362 ++ new WithNKBL1D(64, ways = 4) 363 ++ new BaseConfig(n) 364) 365