1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config._ 20import chisel3._ 21import chisel3.util._ 22import device.{EnableJtag, XSDebugModuleParams} 23import freechips.rocketchip.devices.debug._ 24import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 25import system._ 26import utility._ 27import utils._ 28import huancun._ 29import xiangshan._ 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36import coupledL2._ 37import xiangshan.frontend.icache.ICacheParameters 38 39class BaseConfig(n: Int) extends Config((site, here, up) => { 40 case XLen => 64 41 case DebugOptionsKey => DebugOptions() 42 case SoCParamsKey => SoCParameters() 43 case PMParameKey => PMParameters() 44 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 45 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 46 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 47 case JtagDTMKey => JtagDTMKey 48 case MaxHartIdBits => 2 49 case EnableJtag => true.B 50}) 51 52// Synthesizable minimal XiangShan 53// * It is still an out-of-order, super-scalaer arch 54// * L1 cache included 55// * L2 cache NOT included 56// * L3 cache included 57class MinimalConfig(n: Int = 1) extends Config( 58 new BaseConfig(n).alter((site, here, up) => { 59 case XSTileKey => up(XSTileKey).map( 60 _.copy( 61 DecodeWidth = 2, 62 RenameWidth = 2, 63 CommitWidth = 2, 64 FetchWidth = 4, 65 NRPhyRegs = 96, 66 IntPhyRegs = 96, 67 VfPhyRegs = 96, 68 VirtualLoadQueueSize = 16, 69 LoadQueueRARSize = 16, 70 LoadQueueRAWSize = 12, 71 LoadQueueReplaySize = 8, 72 LoadUncacheBufferSize = 8, 73 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 74 RollbackGroupSize = 8, 75 StoreQueueSize = 12, 76 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 77 StoreQueueForwardWithMask = true, 78 RobSize = 32, 79 FtqSize = 8, 80 IBufSize = 16, 81 StoreBufferSize = 4, 82 StoreBufferThreshold = 3, 83 dpParams = DispatchParameters( 84 IntDqSize = 12, 85 FpDqSize = 12, 86 LsDqSize = 12, 87 IntDqDeqWidth = 4, 88 FpDqDeqWidth = 4, 89 LsDqDeqWidth = 4 90 ), 91 intPreg = IntPregParams( 92 numEntries = 128, 93 numRead = 14, 94 numWrite = 8, 95 ), 96 vfPreg = VfPregParams( 97 numEntries = 128, 98 numRead = 14, 99 numWrite = 8, 100 ), 101 icacheParameters = ICacheParameters( 102 nSets = 64, // 16KB ICache 103 tagECC = Some("parity"), 104 dataECC = Some("parity"), 105 replacer = Some("setplru"), 106 nMissEntries = 2, 107 nReleaseEntries = 1, 108 nProbeEntries = 2, 109 nPrefetchEntries = 2, 110 nPrefBufferEntries = 32, 111 hasPrefetch = true 112 ), 113 dcacheParametersOpt = Some(DCacheParameters( 114 nSets = 64, // 32KB DCache 115 nWays = 8, 116 tagECC = Some("secded"), 117 dataECC = Some("secded"), 118 replacer = Some("setplru"), 119 nMissEntries = 4, 120 nProbeEntries = 4, 121 nReleaseEntries = 8, 122 )), 123 EnableBPD = false, // disable TAGE 124 EnableLoop = false, 125 itlbParameters = TLBParameters( 126 name = "itlb", 127 fetchi = true, 128 useDmode = false, 129 normalReplacer = Some("plru"), 130 superReplacer = Some("plru"), 131 normalNWays = 4, 132 normalNSets = 1, 133 superNWays = 2 134 ), 135 ldtlbParameters = TLBParameters( 136 name = "ldtlb", 137 normalNSets = 16, // when da or sa 138 normalNWays = 1, // when fa or sa 139 normalAssociative = "sa", 140 normalReplacer = Some("setplru"), 141 superNWays = 4, 142 normalAsVictim = true, 143 partialStaticPMP = true, 144 outsideRecvFlush = true, 145 outReplace = false 146 ), 147 sttlbParameters = TLBParameters( 148 name = "sttlb", 149 normalNSets = 16, // when da or sa 150 normalNWays = 1, // when fa or sa 151 normalAssociative = "sa", 152 normalReplacer = Some("setplru"), 153 normalAsVictim = true, 154 superNWays = 4, 155 partialStaticPMP = true, 156 outsideRecvFlush = true, 157 outReplace = false 158 ), 159 pftlbParameters = TLBParameters( 160 name = "pftlb", 161 normalNSets = 16, // when da or sa 162 normalNWays = 1, // when fa or sa 163 normalAssociative = "sa", 164 normalReplacer = Some("setplru"), 165 normalAsVictim = true, 166 superNWays = 4, 167 partialStaticPMP = true, 168 outsideRecvFlush = true, 169 outReplace = false 170 ), 171 btlbParameters = TLBParameters( 172 name = "btlb", 173 normalNSets = 1, 174 normalNWays = 8, 175 superNWays = 2 176 ), 177 l2tlbParameters = L2TLBParameters( 178 l1Size = 4, 179 l2nSets = 4, 180 l2nWays = 4, 181 l3nSets = 4, 182 l3nWays = 8, 183 spSize = 2, 184 ), 185 L2CacheParamsOpt = Some(L2Param( 186 name = "L2", 187 ways = 8, 188 sets = 128, 189 echoField = Seq(huancun.DirtyField()), 190 prefetch = None 191 )), 192 L2NBanks = 2, 193 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 194 ) 195 ) 196 case SoCParamsKey => 197 val tiles = site(XSTileKey) 198 up(SoCParamsKey).copy( 199 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 200 sets = 1024, 201 inclusive = false, 202 clientCaches = tiles.map{ core => 203 val clientDirBytes = tiles.map{ t => 204 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 205 }.sum 206 val l2params = core.L2CacheParamsOpt.get.toCacheParams 207 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 208 }, 209 simulation = !site(DebugOptionsKey).FPGAPlatform 210 )), 211 L3NBanks = 1 212 ) 213 }) 214) 215 216// Non-synthesizable MinimalConfig, for fast simulation only 217class MinimalSimConfig(n: Int = 1) extends Config( 218 new MinimalConfig(n).alter((site, here, up) => { 219 case XSTileKey => up(XSTileKey).map(_.copy( 220 dcacheParametersOpt = None, 221 softPTW = true 222 )) 223 case SoCParamsKey => up(SoCParamsKey).copy( 224 L3CacheParamsOpt = None 225 ) 226 }) 227) 228 229class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 230 case XSTileKey => 231 val sets = n * 1024 / ways / 64 232 up(XSTileKey).map(_.copy( 233 dcacheParametersOpt = Some(DCacheParameters( 234 nSets = sets, 235 nWays = ways, 236 tagECC = Some("secded"), 237 dataECC = Some("secded"), 238 replacer = Some("setplru"), 239 nMissEntries = 16, 240 nProbeEntries = 8, 241 nReleaseEntries = 18 242 )) 243 )) 244}) 245 246class WithNKBL2 247( 248 n: Int, 249 ways: Int = 8, 250 inclusive: Boolean = true, 251 banks: Int = 1, 252 alwaysReleaseData: Boolean = false 253) extends Config((site, here, up) => { 254 case XSTileKey => 255 val upParams = up(XSTileKey) 256 val l2sets = n * 1024 / banks / ways / 64 257 upParams.map(p => p.copy( 258 L2CacheParamsOpt = Some(L2Param( 259 name = "L2", 260 ways = ways, 261 sets = l2sets, 262 clientCaches = Seq(L1Param( 263 "dcache", 264 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 265 ways = p.dcacheParametersOpt.get.nWays + 2, 266 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 267 )), 268 echoField = Seq(huancun.DirtyField()), 269 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 270 )), 271 L2NBanks = banks 272 )) 273}) 274 275class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 276 case SoCParamsKey => 277 val sets = n * 1024 / banks / ways / 64 278 val tiles = site(XSTileKey) 279 val clientDirBytes = tiles.map{ t => 280 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 281 }.sum 282 up(SoCParamsKey).copy( 283 L3NBanks = banks, 284 L3CacheParamsOpt = Some(HCCacheParameters( 285 name = "L3", 286 level = 3, 287 ways = ways, 288 sets = sets, 289 inclusive = inclusive, 290 clientCaches = tiles.map{ core => 291 val l2params = core.L2CacheParamsOpt.get.toCacheParams 292 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 293 }, 294 enablePerf = true, 295 ctrl = Some(CacheCtrl( 296 address = 0x39000000, 297 numCores = tiles.size 298 )), 299 sramClkDivBy2 = true, 300 sramDepthDiv = 4, 301 tagECC = Some("secded"), 302 dataECC = Some("secded"), 303 simulation = !site(DebugOptionsKey).FPGAPlatform 304 )) 305 ) 306}) 307 308class WithL3DebugConfig extends Config( 309 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 310) 311 312class MinimalL3DebugConfig(n: Int = 1) extends Config( 313 new WithL3DebugConfig ++ new MinimalConfig(n) 314) 315 316class DefaultL3DebugConfig(n: Int = 1) extends Config( 317 new WithL3DebugConfig ++ new BaseConfig(n) 318) 319 320class MinimalAliasDebugConfig(n: Int = 1) extends Config( 321 new WithNKBL3(512, inclusive = false) ++ 322 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 323 new WithNKBL1D(128) ++ 324 new MinimalConfig(n) 325) 326 327class MediumConfig(n: Int = 1) extends Config( 328 new WithNKBL3(4096, inclusive = false, banks = 4) 329 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 330 ++ new WithNKBL1D(128) 331 ++ new BaseConfig(n) 332) 333 334class DefaultConfig(n: Int = 1) extends Config( 335 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 336 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 337 ++ new WithNKBL1D(128) 338 ++ new BaseConfig(n) 339) 340