1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import xiangshan.frontend.icache.ICacheParameters 27import freechips.rocketchip.devices.debug._ 28import freechips.rocketchip.tile.MaxHartIdBits 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.backend.exu.ExuParameters 31import xiangshan.cache.DCacheParameters 32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 33import device.{EnableJtag, XSDebugModuleParams} 34import huancun._ 35 36class BaseConfig(n: Int) extends Config((site, here, up) => { 37 case XLen => 64 38 case DebugOptionsKey => DebugOptions() 39 case SoCParamsKey => SoCParameters() 40 case PMParameKey => PMParameters() 41 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 42 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 43 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 44 case JtagDTMKey => JtagDTMKey 45 case MaxHartIdBits => 2 46 case EnableJtag => true.B 47}) 48 49// Synthesizable minimal XiangShan 50// * It is still an out-of-order, super-scalaer arch 51// * L1 cache included 52// * L2 cache NOT included 53// * L3 cache included 54class MinimalConfig(n: Int = 1) extends Config( 55 new BaseConfig(n).alter((site, here, up) => { 56 case XSTileKey => up(XSTileKey).map( 57 _.copy( 58 DecodeWidth = 2, 59 RenameWidth = 2, 60 FetchWidth = 4, 61 IssQueSize = 8, 62 NRPhyRegs = 64, 63 LoadQueueSize = 16, 64 StoreQueueSize = 12, 65 RobSize = 32, 66 FtqSize = 8, 67 IBufSize = 16, 68 StoreBufferSize = 4, 69 StoreBufferThreshold = 3, 70 dpParams = DispatchParameters( 71 IntDqSize = 12, 72 FpDqSize = 12, 73 LsDqSize = 12, 74 IntDqDeqWidth = 4, 75 FpDqDeqWidth = 4, 76 LsDqDeqWidth = 4 77 ), 78 exuParameters = ExuParameters( 79 JmpCnt = 1, 80 AluCnt = 2, 81 MulCnt = 0, 82 MduCnt = 1, 83 FmacCnt = 1, 84 FmiscCnt = 1, 85 FmiscDivSqrtCnt = 0, 86 LduCnt = 2, 87 StuCnt = 2 88 ), 89 icacheParameters = ICacheParameters( 90 nSets = 64, // 16KB ICache 91 tagECC = Some("parity"), 92 dataECC = Some("parity"), 93 replacer = Some("setplru"), 94 nMissEntries = 2, 95 nReleaseEntries = 1, 96 nProbeEntries = 2, 97 nPrefetchEntries = 2, 98 hasPrefetch = false 99 ), 100 dcacheParametersOpt = Some(DCacheParameters( 101 nSets = 64, // 32KB DCache 102 nWays = 8, 103 tagECC = Some("secded"), 104 dataECC = Some("secded"), 105 replacer = Some("setplru"), 106 nMissEntries = 4, 107 nProbeEntries = 4, 108 nReleaseEntries = 8, 109 )), 110 EnableBPD = false, // disable TAGE 111 EnableLoop = false, 112 itlbParameters = TLBParameters( 113 name = "itlb", 114 fetchi = true, 115 useDmode = false, 116 normalReplacer = Some("plru"), 117 superReplacer = Some("plru"), 118 normalNWays = 4, 119 normalNSets = 1, 120 superNWays = 2 121 ), 122 ldtlbParameters = TLBParameters( 123 name = "ldtlb", 124 normalNSets = 16, // when da or sa 125 normalNWays = 1, // when fa or sa 126 normalAssociative = "sa", 127 normalReplacer = Some("setplru"), 128 superNWays = 4, 129 normalAsVictim = true, 130 partialStaticPMP = true, 131 outsideRecvFlush = true, 132 outReplace = false 133 ), 134 sttlbParameters = TLBParameters( 135 name = "sttlb", 136 normalNSets = 16, // when da or sa 137 normalNWays = 1, // when fa or sa 138 normalAssociative = "sa", 139 normalReplacer = Some("setplru"), 140 normalAsVictim = true, 141 superNWays = 4, 142 partialStaticPMP = true, 143 outsideRecvFlush = true, 144 outReplace = false 145 ), 146 btlbParameters = TLBParameters( 147 name = "btlb", 148 normalNSets = 1, 149 normalNWays = 8, 150 superNWays = 2 151 ), 152 l2tlbParameters = L2TLBParameters( 153 l1Size = 4, 154 l2nSets = 4, 155 l2nWays = 4, 156 l3nSets = 4, 157 l3nWays = 8, 158 spSize = 2, 159 ), 160 L2CacheParamsOpt = None // remove L2 Cache 161 ) 162 ) 163 case SoCParamsKey => 164 val tiles = site(XSTileKey) 165 up(SoCParamsKey).copy( 166 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 167 sets = 1024, 168 inclusive = false, 169 clientCaches = tiles.map{ p => 170 CacheParameters( 171 "dcache", 172 sets = 2 * p.dcacheParametersOpt.get.nSets, 173 ways = p.dcacheParametersOpt.get.nWays + 2, 174 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets), 175 aliasBitsOpt = None 176 ) 177 }, 178 simulation = !site(DebugOptionsKey).FPGAPlatform 179 )), 180 L3NBanks = 1 181 ) 182 }) 183) 184 185// Non-synthesizable MinimalConfig, for fast simulation only 186class MinimalSimConfig(n: Int = 1) extends Config( 187 new MinimalConfig(n).alter((site, here, up) => { 188 case XSTileKey => up(XSTileKey).map(_.copy( 189 dcacheParametersOpt = None, 190 softPTW = true 191 )) 192 case SoCParamsKey => up(SoCParamsKey).copy( 193 L3CacheParamsOpt = None 194 ) 195 }) 196) 197 198class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 199 case XSTileKey => 200 val sets = n * 1024 / ways / 64 201 up(XSTileKey).map(_.copy( 202 dcacheParametersOpt = Some(DCacheParameters( 203 nSets = sets, 204 nWays = ways, 205 tagECC = Some("secded"), 206 dataECC = Some("secded"), 207 replacer = Some("setplru"), 208 nMissEntries = 16, 209 nProbeEntries = 8, 210 nReleaseEntries = 18 211 )) 212 )) 213}) 214 215class WithNKBL2 216( 217 n: Int, 218 ways: Int = 8, 219 inclusive: Boolean = true, 220 banks: Int = 1, 221 alwaysReleaseData: Boolean = false 222) extends Config((site, here, up) => { 223 case XSTileKey => 224 val upParams = up(XSTileKey) 225 val l2sets = n * 1024 / banks / ways / 64 226 upParams.map(p => p.copy( 227 L2CacheParamsOpt = Some(HCCacheParameters( 228 name = "L2", 229 level = 2, 230 ways = ways, 231 sets = l2sets, 232 inclusive = inclusive, 233 alwaysReleaseData = alwaysReleaseData, 234 clientCaches = Seq(CacheParameters( 235 "dcache", 236 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 237 ways = p.dcacheParametersOpt.get.nWays + 2, 238 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets / banks), 239 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 240 )), 241 reqField = Seq(PreferCacheField()), 242 echoField = Seq(DirtyField()), 243 prefetch = Some(huancun.prefetch.BOPParameters()), 244 enablePerf = true, 245 sramDepthDiv = 2, 246 tagECC = Some("secded"), 247 dataECC = Some("secded"), 248 simulation = !site(DebugOptionsKey).FPGAPlatform 249 )), 250 L2NBanks = banks 251 )) 252}) 253 254class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 255 case SoCParamsKey => 256 val sets = n * 1024 / banks / ways / 64 257 val tiles = site(XSTileKey) 258 val clientDirBytes = tiles.map{ t => 259 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 260 }.sum 261 up(SoCParamsKey).copy( 262 L3NBanks = banks, 263 L3CacheParamsOpt = Some(HCCacheParameters( 264 name = "L3", 265 level = 3, 266 ways = ways, 267 sets = sets, 268 inclusive = inclusive, 269 clientCaches = tiles.map{ core => 270 val l2params = core.L2CacheParamsOpt.get.toCacheParams 271 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 272 }, 273 enablePerf = true, 274 ctrl = Some(CacheCtrl( 275 address = 0x39000000, 276 numCores = tiles.size 277 )), 278 sramClkDivBy2 = true, 279 sramDepthDiv = 4, 280 tagECC = Some("secded"), 281 dataECC = Some("secded"), 282 simulation = !site(DebugOptionsKey).FPGAPlatform 283 )) 284 ) 285}) 286 287class WithL3DebugConfig extends Config( 288 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 289) 290 291class MinimalL3DebugConfig(n: Int = 1) extends Config( 292 new WithL3DebugConfig ++ new MinimalConfig(n) 293) 294 295class DefaultL3DebugConfig(n: Int = 1) extends Config( 296 new WithL3DebugConfig ++ new BaseConfig(n) 297) 298 299class MinimalAliasDebugConfig(n: Int = 1) extends Config( 300 new WithNKBL3(512, inclusive = false) ++ 301 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 302 new WithNKBL1D(128) ++ 303 new MinimalConfig(n) 304) 305 306class MediumConfig(n: Int = 1) extends Config( 307 new WithNKBL3(4096, inclusive = false, banks = 4) 308 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 309 ++ new WithNKBL1D(128) 310 ++ new BaseConfig(n) 311) 312 313class DefaultConfig(n: Int = 1) extends Config( 314 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 315 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 316 ++ new WithNKBL1D(128) 317 ++ new BaseConfig(n) 318) 319