1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import xiangshan.frontend.ICacheParameters 27import freechips.rocketchip.devices.debug._ 28import freechips.rocketchip.tile.MaxHartIdBits 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.backend.exu.ExuParameters 31import xiangshan.cache.DCacheParameters 32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 33import device.{EnableJtag, XSDebugModuleParams} 34import huancun._ 35 36class BaseConfig(n: Int) extends Config((site, here, up) => { 37 case XLen => 64 38 case DebugOptionsKey => DebugOptions() 39 case SoCParamsKey => SoCParameters( 40 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 41 ) 42 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 43 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 44 case JtagDTMKey => JtagDTMKey 45 case MaxHartIdBits => 2 46 case EnableJtag => false.B 47}) 48 49// Synthesizable minimal XiangShan 50// * It is still an out-of-order, super-scalaer arch 51// * L1 cache included 52// * L2 cache NOT included 53// * L3 cache included 54class MinimalConfig(n: Int = 1) extends Config( 55 new BaseConfig(n).alter((site, here, up) => { 56 case SoCParamsKey => up(SoCParamsKey).copy( 57 cores = up(SoCParamsKey).cores.map(_.copy( 58 DecodeWidth = 2, 59 RenameWidth = 2, 60 FetchWidth = 4, 61 IssQueSize = 8, 62 NRPhyRegs = 64, 63 LoadQueueSize = 16, 64 StoreQueueSize = 12, 65 RoqSize = 32, 66 BrqSize = 8, 67 FtqSize = 8, 68 IBufSize = 16, 69 StoreBufferSize = 4, 70 StoreBufferThreshold = 3, 71 dpParams = DispatchParameters( 72 IntDqSize = 12, 73 FpDqSize = 12, 74 LsDqSize = 12, 75 IntDqDeqWidth = 4, 76 FpDqDeqWidth = 4, 77 LsDqDeqWidth = 4 78 ), 79 exuParameters = ExuParameters( 80 JmpCnt = 1, 81 AluCnt = 2, 82 MulCnt = 0, 83 MduCnt = 1, 84 FmacCnt = 1, 85 FmiscCnt = 1, 86 FmiscDivSqrtCnt = 0, 87 LduCnt = 2, 88 StuCnt = 2 89 ), 90 icacheParameters = ICacheParameters( 91 nSets = 64, // 16KB ICache 92 tagECC = Some("parity"), 93 dataECC = Some("parity"), 94 replacer = Some("setplru"), 95 nMissEntries = 2 96 ), 97 dcacheParameters = DCacheParameters( 98 nSets = 64, // 128KB DCache 99 nWays = 8, 100 tagECC = Some("secded"), 101 dataECC = Some("secded"), 102 replacer = Some("setplru"), 103 nMissEntries = 4, 104 nProbeEntries = 4, 105 nReleaseEntries = 4, 106 nStoreReplayEntries = 4, 107 ), 108 EnableBPD = false, // disable TAGE 109 EnableLoop = false, 110 itlbParameters = TLBParameters( 111 name = "itlb", 112 fetchi = true, 113 useDmode = false, 114 sameCycle = true, 115 normalReplacer = Some("plru"), 116 superReplacer = Some("plru"), 117 normalNWays = 4, 118 normalNSets = 1, 119 superNWays = 2, 120 shouldBlock = true 121 ), 122 ldtlbParameters = TLBParameters( 123 name = "ldtlb", 124 normalNSets = 4, // when da or sa 125 normalNWays = 1, // when fa or sa 126 normalAssociative = "sa", 127 normalReplacer = Some("setplru"), 128 superNWays = 4, 129 normalAsVictim = true, 130 outReplace = true 131 ), 132 sttlbParameters = TLBParameters( 133 name = "sttlb", 134 normalNSets = 4, // when da or sa 135 normalNWays = 1, // when fa or sa 136 normalAssociative = "sa", 137 normalReplacer = Some("setplru"), 138 normalAsVictim = true, 139 superNWays = 4, 140 outReplace = true 141 ), 142 btlbParameters = TLBParameters( 143 name = "btlb", 144 normalNSets = 1, 145 normalNWays = 8, 146 superNWays = 2 147 ), 148 l2tlbParameters = L2TLBParameters( 149 l1Size = 4, 150 l2nSets = 4, 151 l2nWays = 4, 152 l3nSets = 4, 153 l3nWays = 8, 154 spSize = 2, 155 missQueueSize = 8 156 ), 157 useFakeL2Cache = true, // disable L2 Cache 158 )), 159 L3CacheParams = up(SoCParamsKey).L3CacheParams.copy( 160 sets = 1024 161 ), 162 L3NBanks = 1 163 ) 164 }) 165) 166 167// Non-synthesizable MinimalConfig, for fast simulation only 168class MinimalSimConfig(n: Int = 1) extends Config( 169 new MinimalConfig(n).alter((site, here, up) => { 170 case SoCParamsKey => up(SoCParamsKey).copy( 171 cores = up(SoCParamsKey).cores.map(_.copy( 172 useFakeDCache = true, 173 useFakePTW = true, 174 useFakeL1plusCache = true, 175 )), 176 useFakeL3Cache = true 177 ) 178 }) 179) 180 181class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 182 case SoCParamsKey => 183 val upParams = up(SoCParamsKey) 184 val sets = n * 1024 / ways / 64 185 upParams.copy(cores = upParams.cores.map(p => p.copy( 186 dcacheParameters = p.dcacheParameters.copy( 187 nSets = sets, 188 nWays = ways 189 ) 190 ))) 191} 192) 193 194class WithNKBL2(n: Int, ways: Int = 8, inclusive: Boolean = true, alwaysReleaseData: Boolean = false) extends Config((site, here, up) => { 195 case SoCParamsKey => 196 val upParams = up(SoCParamsKey) 197 val l2sets = n * 1024 / ways / 64 198 upParams.copy( 199 cores = upParams.cores.map(p => p.copy( 200 L2CacheParams = HCCacheParameters( 201 name = "L2", 202 level = 2, 203 ways = ways, 204 sets = l2sets, 205 inclusive = inclusive, 206 alwaysReleaseData = alwaysReleaseData, 207 clientCaches = Seq(CacheParameters( 208 "dcache", 209 sets = 2 * p.dcacheParameters.nSets, 210 ways = p.dcacheParameters.nWays + 2, 211 aliasBitsOpt = p.dcacheParameters.aliasBitsOpt 212 )), 213 reqField = Seq(PreferCacheField()), 214 echoField = Seq(DirtyField()), 215 prefetch = Some(huancun.prefetch.BOPParameters()), 216 enablePerf = true 217 ), 218 useFakeL2Cache = false, 219 useFakeDCache = false, 220 useFakePTW = false, 221 useFakeL1plusCache = false 222 )) 223 ) 224}) 225 226class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 227 case SoCParamsKey => 228 val upParams = up(SoCParamsKey) 229 val sets = n * 1024 / banks / ways / 64 230 upParams.copy( 231 L3NBanks = banks, 232 L3CacheParams = HCCacheParameters( 233 name = "L3", 234 level = 3, 235 ways = ways, 236 sets = sets, 237 inclusive = inclusive, 238 clientCaches = upParams.cores.map{ core => 239 val l2params = core.L2CacheParams.toCacheParams 240 l2params.copy(ways = 2 * l2params.ways) 241 }, 242 enablePerf = true 243 ) 244 ) 245}) 246 247class WithL3DebugConfig extends Config( 248 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 249) 250 251class MinimalL3DebugConfig(n: Int = 1) extends Config( 252 new WithL3DebugConfig ++ new MinimalConfig(n) 253) 254 255class DefaultL3DebugConfig(n: Int = 1) extends Config( 256 new WithL3DebugConfig ++ new BaseConfig(n) 257) 258 259class MinimalAliasDebugConfig(n: Int = 1) extends Config( 260 new WithNKBL3(512, inclusive = false) ++ 261 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 262 new WithNKBL1D(128) ++ 263 new MinimalConfig(n) 264) 265 266class DefaultConfig(n: Int = 1) extends Config( 267 new WithNKBL3(4096, inclusive = false, banks = 4) 268 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 269 ++ new WithNKBL1D(128) 270 ++ new BaseConfig(n) 271) 272