1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import xiangshan.frontend.icache.ICacheParameters 43 44class BaseConfig(n: Int) extends Config((site, here, up) => { 45 case XLen => 64 46 case DebugOptionsKey => DebugOptions() 47 case SoCParamsKey => SoCParameters() 48 case PMParameKey => PMParameters() 49 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 50 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 51 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 52 case JtagDTMKey => JtagDTMKey 53 case MaxHartIdBits => 2 54 case EnableJtag => true.B 55}) 56 57// Synthesizable minimal XiangShan 58// * It is still an out-of-order, super-scalaer arch 59// * L1 cache included 60// * L2 cache NOT included 61// * L3 cache included 62class MinimalConfig(n: Int = 1) extends Config( 63 new BaseConfig(n).alter((site, here, up) => { 64 case XSTileKey => up(XSTileKey).map( 65 _.copy( 66 DecodeWidth = 2, 67 RenameWidth = 2, 68 CommitWidth = 2, 69 FetchWidth = 4, 70 VirtualLoadQueueSize = 16, 71 LoadQueueRARSize = 16, 72 LoadQueueRAWSize = 12, 73 LoadQueueReplaySize = 8, 74 LoadUncacheBufferSize = 8, 75 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 76 RollbackGroupSize = 8, 77 StoreQueueSize = 12, 78 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 79 StoreQueueForwardWithMask = true, 80 RobSize = 32, 81 RabSize = 32, 82 FtqSize = 8, 83 IBufSize = 16, 84 StoreBufferSize = 4, 85 StoreBufferThreshold = 3, 86 IssueQueueSize = 8, 87 dpParams = DispatchParameters( 88 IntDqSize = 12, 89 FpDqSize = 12, 90 LsDqSize = 12, 91 IntDqDeqWidth = 4, 92 FpDqDeqWidth = 4, 93 LsDqDeqWidth = 4 94 ), 95 intPreg = IntPregParams( 96 numEntries = 64, 97 numRead = None, 98 numWrite = None, 99 ), 100 vfPreg = VfPregParams( 101 numEntries = 192, 102 numRead = None, 103 numWrite = None, 104 ), 105 icacheParameters = ICacheParameters( 106 nSets = 64, // 16KB ICache 107 tagECC = Some("parity"), 108 dataECC = Some("parity"), 109 replacer = Some("setplru"), 110 nMissEntries = 2, 111 nReleaseEntries = 1, 112 nProbeEntries = 2, 113 // fdip 114 enableICachePrefetch = true, 115 prefetchToL1 = false, 116 ), 117 dcacheParametersOpt = Some(DCacheParameters( 118 nSets = 64, // 32KB DCache 119 nWays = 8, 120 tagECC = Some("secded"), 121 dataECC = Some("secded"), 122 replacer = Some("setplru"), 123 nMissEntries = 4, 124 nProbeEntries = 4, 125 nReleaseEntries = 8, 126 nMaxPrefetchEntry = 2, 127 )), 128 EnableBPD = false, // disable TAGE 129 EnableLoop = false, 130 itlbParameters = TLBParameters( 131 name = "itlb", 132 fetchi = true, 133 useDmode = false, 134 NWays = 4, 135 ), 136 ldtlbParameters = TLBParameters( 137 name = "ldtlb", 138 NWays = 4, 139 partialStaticPMP = true, 140 outsideRecvFlush = true, 141 outReplace = false 142 ), 143 sttlbParameters = TLBParameters( 144 name = "sttlb", 145 NWays = 4, 146 partialStaticPMP = true, 147 outsideRecvFlush = true, 148 outReplace = false 149 ), 150 pftlbParameters = TLBParameters( 151 name = "pftlb", 152 NWays = 4, 153 partialStaticPMP = true, 154 outsideRecvFlush = true, 155 outReplace = false 156 ), 157 btlbParameters = TLBParameters( 158 name = "btlb", 159 NWays = 4, 160 ), 161 l2tlbParameters = L2TLBParameters( 162 l1Size = 4, 163 l2nSets = 4, 164 l2nWays = 4, 165 l3nSets = 4, 166 l3nWays = 8, 167 spSize = 2, 168 ), 169 L2CacheParamsOpt = Some(L2Param( 170 name = "L2", 171 ways = 8, 172 sets = 128, 173 echoField = Seq(huancun.DirtyField()), 174 prefetch = None 175 )), 176 L2NBanks = 2, 177 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 178 ) 179 ) 180 case SoCParamsKey => 181 val tiles = site(XSTileKey) 182 up(SoCParamsKey).copy( 183 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 184 sets = 1024, 185 inclusive = false, 186 clientCaches = tiles.map{ core => 187 val clientDirBytes = tiles.map{ t => 188 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 189 }.sum 190 val l2params = core.L2CacheParamsOpt.get.toCacheParams 191 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 192 }, 193 simulation = !site(DebugOptionsKey).FPGAPlatform, 194 prefetch = None 195 )), 196 L3NBanks = 1 197 ) 198 }) 199) 200 201// Non-synthesizable MinimalConfig, for fast simulation only 202class MinimalSimConfig(n: Int = 1) extends Config( 203 new MinimalConfig(n).alter((site, here, up) => { 204 case XSTileKey => up(XSTileKey).map(_.copy( 205 dcacheParametersOpt = None, 206 softPTW = true 207 )) 208 case SoCParamsKey => up(SoCParamsKey).copy( 209 L3CacheParamsOpt = None 210 ) 211 }) 212) 213 214class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 215 case XSTileKey => 216 val sets = n * 1024 / ways / 64 217 up(XSTileKey).map(_.copy( 218 dcacheParametersOpt = Some(DCacheParameters( 219 nSets = sets, 220 nWays = ways, 221 tagECC = Some("secded"), 222 dataECC = Some("secded"), 223 replacer = Some("setplru"), 224 nMissEntries = 16, 225 nProbeEntries = 8, 226 nReleaseEntries = 18, 227 nMaxPrefetchEntry = 6, 228 )) 229 )) 230}) 231 232class WithNKBL2 233( 234 n: Int, 235 ways: Int = 8, 236 inclusive: Boolean = true, 237 banks: Int = 1 238) extends Config((site, here, up) => { 239 case XSTileKey => 240 val upParams = up(XSTileKey) 241 val l2sets = n * 1024 / banks / ways / 64 242 upParams.map(p => p.copy( 243 L2CacheParamsOpt = Some(L2Param( 244 name = "L2", 245 ways = ways, 246 sets = l2sets, 247 clientCaches = Seq(L1Param( 248 "dcache", 249 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 250 ways = p.dcacheParametersOpt.get.nWays + 2, 251 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 252 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)) 253 )), 254 reqField = Seq(utility.ReqSourceField()), 255 echoField = Seq(huancun.DirtyField()), 256 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 257 )), 258 L2NBanks = banks 259 )) 260}) 261 262class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 263 case SoCParamsKey => 264 val sets = n * 1024 / banks / ways / 64 265 val tiles = site(XSTileKey) 266 val clientDirBytes = tiles.map{ t => 267 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 268 }.sum 269 up(SoCParamsKey).copy( 270 L3NBanks = banks, 271 L3CacheParamsOpt = Some(HCCacheParameters( 272 name = "L3", 273 level = 3, 274 ways = ways, 275 sets = sets, 276 inclusive = inclusive, 277 clientCaches = tiles.map{ core => 278 val l2params = core.L2CacheParamsOpt.get.toCacheParams 279 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 280 }, 281 enablePerf = true, 282 ctrl = Some(CacheCtrl( 283 address = 0x39000000, 284 numCores = tiles.size 285 )), 286 reqField = Seq(utility.ReqSourceField()), 287 sramClkDivBy2 = true, 288 sramDepthDiv = 4, 289 tagECC = Some("secded"), 290 dataECC = Some("secded"), 291 simulation = !site(DebugOptionsKey).FPGAPlatform, 292 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()) 293 )) 294 ) 295}) 296 297class WithL3DebugConfig extends Config( 298 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 299) 300 301class MinimalL3DebugConfig(n: Int = 1) extends Config( 302 new WithL3DebugConfig ++ new MinimalConfig(n) 303) 304 305class DefaultL3DebugConfig(n: Int = 1) extends Config( 306 new WithL3DebugConfig ++ new BaseConfig(n) 307) 308 309class WithFuzzer extends Config((site, here, up) => { 310 case DebugOptionsKey => up(DebugOptionsKey).copy( 311 EnablePerfDebug = false, 312 ) 313 case SoCParamsKey => up(SoCParamsKey).copy( 314 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 315 enablePerf = false, 316 )), 317 ) 318 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 319 p.copy( 320 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 321 enablePerf = false, 322 )), 323 ) 324 } 325}) 326 327class MinimalAliasDebugConfig(n: Int = 1) extends Config( 328 new WithNKBL3(512, inclusive = false) ++ 329 new WithNKBL2(256, inclusive = false) ++ 330 new WithNKBL1D(128) ++ 331 new MinimalConfig(n) 332) 333 334class MediumConfig(n: Int = 1) extends Config( 335 new WithNKBL3(4096, inclusive = false, banks = 4) 336 ++ new WithNKBL2(512, inclusive = false) 337 ++ new WithNKBL1D(128) 338 ++ new BaseConfig(n) 339) 340 341class FuzzConfig(dummy: Int = 0) extends Config( 342 new WithFuzzer 343 ++ new DefaultConfig(1) 344) 345 346class DefaultConfig(n: Int = 1) extends Config( 347 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 348 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4) 349 ++ new WithNKBL1D(128) 350 ++ new BaseConfig(n) 351) 352