1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import openLLC.{OpenLLCParam} 35import xiangshan._ 36import xiangshan.backend.dispatch.DispatchParameters 37import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 38import xiangshan.cache.DCacheParameters 39import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 40import device.{EnableJtag, XSDebugModuleParams} 41import huancun._ 42import coupledL2._ 43import coupledL2.prefetch._ 44import xiangshan.frontend.icache.ICacheParameters 45 46class BaseConfig(n: Int) extends Config((site, here, up) => { 47 case XLen => 64 48 case DebugOptionsKey => DebugOptions() 49 case SoCParamsKey => SoCParameters() 50 case PMParameKey => PMParameters() 51 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 52 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 53 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 54 case JtagDTMKey => JtagDTMKey 55 case MaxHartIdBits => log2Up(n) max 6 56 case EnableJtag => true.B 57}) 58 59// Synthesizable minimal XiangShan 60// * It is still an out-of-order, super-scalaer arch 61// * L1 cache included 62// * L2 cache NOT included 63// * L3 cache included 64class MinimalConfig(n: Int = 1) extends Config( 65 new BaseConfig(n).alter((site, here, up) => { 66 case XSTileKey => up(XSTileKey).map( 67 p => p.copy( 68 DecodeWidth = 6, 69 RenameWidth = 6, 70 RobCommitWidth = 8, 71 FetchWidth = 4, 72 VirtualLoadQueueSize = 24, 73 LoadQueueRARSize = 24, 74 LoadQueueRAWSize = 12, 75 LoadQueueReplaySize = 24, 76 LoadUncacheBufferSize = 8, 77 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 78 RollbackGroupSize = 8, 79 StoreQueueSize = 20, 80 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 81 StoreQueueForwardWithMask = true, 82 // ============ VLSU ============ 83 VlMergeBufferSize = 16, 84 VsMergeBufferSize = 8, 85 UopWritebackWidth = 2, 86 // ============================== 87 RobSize = 48, 88 RabSize = 96, 89 FtqSize = 8, 90 IBufSize = 24, 91 IBufNBank = 6, 92 StoreBufferSize = 4, 93 StoreBufferThreshold = 3, 94 IssueQueueSize = 10, 95 IssueQueueCompEntrySize = 4, 96 dpParams = DispatchParameters( 97 IntDqSize = 12, 98 FpDqSize = 12, 99 LsDqSize = 12, 100 IntDqDeqWidth = 8, 101 FpDqDeqWidth = 6, 102 VecDqDeqWidth = 6, 103 LsDqDeqWidth = 6 104 ), 105 intPreg = IntPregParams( 106 numEntries = 64, 107 numRead = None, 108 numWrite = None, 109 ), 110 vfPreg = VfPregParams( 111 numEntries = 160, 112 numRead = None, 113 numWrite = None, 114 ), 115 icacheParameters = ICacheParameters( 116 nSets = 64, // 16KB ICache 117 tagECC = Some("parity"), 118 dataECC = Some("parity"), 119 replacer = Some("setplru"), 120 ), 121 dcacheParametersOpt = Some(DCacheParameters( 122 nSets = 64, // 32KB DCache 123 nWays = 8, 124 tagECC = Some("secded"), 125 dataECC = Some("secded"), 126 replacer = Some("setplru"), 127 nMissEntries = 4, 128 nProbeEntries = 4, 129 nReleaseEntries = 8, 130 nMaxPrefetchEntry = 2, 131 )), 132 // ============ BPU =============== 133 EnableLoop = false, 134 EnableGHistDiff = false, 135 FtbSize = 256, 136 FtbWays = 2, 137 RasSize = 8, 138 RasSpecSize = 16, 139 TageTableInfos = 140 Seq((512, 4, 6), 141 (512, 9, 6), 142 (1024, 19, 6)), 143 SCNRows = 128, 144 SCNTables = 2, 145 SCHistLens = Seq(0, 5), 146 ITTageTableInfos = 147 Seq((256, 4, 7), 148 (256, 8, 7), 149 (512, 16, 7)), 150 // ================================ 151 itlbParameters = TLBParameters( 152 name = "itlb", 153 fetchi = true, 154 useDmode = false, 155 NWays = 4, 156 ), 157 ldtlbParameters = TLBParameters( 158 name = "ldtlb", 159 NWays = 4, 160 partialStaticPMP = true, 161 outsideRecvFlush = true, 162 outReplace = false, 163 lgMaxSize = 4 164 ), 165 sttlbParameters = TLBParameters( 166 name = "sttlb", 167 NWays = 4, 168 partialStaticPMP = true, 169 outsideRecvFlush = true, 170 outReplace = false, 171 lgMaxSize = 4 172 ), 173 hytlbParameters = TLBParameters( 174 name = "hytlb", 175 NWays = 4, 176 partialStaticPMP = true, 177 outsideRecvFlush = true, 178 outReplace = false, 179 lgMaxSize = 4 180 ), 181 pftlbParameters = TLBParameters( 182 name = "pftlb", 183 NWays = 4, 184 partialStaticPMP = true, 185 outsideRecvFlush = true, 186 outReplace = false, 187 lgMaxSize = 4 188 ), 189 btlbParameters = TLBParameters( 190 name = "btlb", 191 NWays = 4, 192 ), 193 l2tlbParameters = L2TLBParameters( 194 l3Size = 4, 195 l2Size = 4, 196 l1nSets = 4, 197 l1nWays = 4, 198 l1ReservedBits = 1, 199 l0nSets = 4, 200 l0nWays = 8, 201 l0ReservedBits = 0, 202 spSize = 4, 203 ), 204 L2CacheParamsOpt = Some(L2Param( 205 name = "L2", 206 ways = 8, 207 sets = 128, 208 echoField = Seq(huancun.DirtyField()), 209 prefetch = Nil, 210 clientCaches = Seq(L1Param( 211 "dcache", 212 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 213 )), 214 hasCMO = p.HasCMO && site(EnableCHI), 215 )), 216 L2NBanks = 2, 217 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 218 ) 219 ) 220 case SoCParamsKey => 221 val tiles = site(XSTileKey) 222 up(SoCParamsKey).copy( 223 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 224 sets = 1024, 225 inclusive = false, 226 clientCaches = tiles.map{ core => 227 val clientDirBytes = tiles.map{ t => 228 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 229 }.sum 230 val l2params = core.L2CacheParamsOpt.get.toCacheParams 231 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 232 }, 233 simulation = !site(DebugOptionsKey).FPGAPlatform, 234 prefetch = None 235 )), 236 L3NBanks = 1 237 ) 238 }) 239) 240 241// Non-synthesizable MinimalConfig, for fast simulation only 242class MinimalSimConfig(n: Int = 1) extends Config( 243 new MinimalConfig(n).alter((site, here, up) => { 244 case XSTileKey => up(XSTileKey).map(_.copy( 245 dcacheParametersOpt = None, 246 softPTW = true 247 )) 248 case SoCParamsKey => up(SoCParamsKey).copy( 249 L3CacheParamsOpt = None 250 ) 251 }) 252) 253 254class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 255 case XSTileKey => 256 val sets = n * 1024 / ways / 64 257 up(XSTileKey).map(_.copy( 258 dcacheParametersOpt = Some(DCacheParameters( 259 nSets = sets, 260 nWays = ways, 261 tagECC = Some("secded"), 262 dataECC = Some("secded"), 263 replacer = Some("setplru"), 264 nMissEntries = 16, 265 nProbeEntries = 8, 266 nReleaseEntries = 18, 267 nMaxPrefetchEntry = 6, 268 )) 269 )) 270}) 271 272class WithNKBL2 273( 274 n: Int, 275 ways: Int = 8, 276 inclusive: Boolean = true, 277 banks: Int = 1, 278 tp: Boolean = true 279) extends Config((site, here, up) => { 280 case XSTileKey => 281 require(inclusive, "L2 must be inclusive") 282 val upParams = up(XSTileKey) 283 val l2sets = n * 1024 / banks / ways / 64 284 upParams.map(p => p.copy( 285 L2CacheParamsOpt = Some(L2Param( 286 name = "L2", 287 ways = ways, 288 sets = l2sets, 289 clientCaches = Seq(L1Param( 290 "dcache", 291 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 292 ways = p.dcacheParametersOpt.get.nWays + 2, 293 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 294 vaddrBitsOpt = Some(p.GPAddrBitsSv48x4 - log2Up(p.dcacheParametersOpt.get.blockBytes)), 295 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 296 )), 297 reqField = Seq(utility.ReqSourceField()), 298 echoField = Seq(huancun.DirtyField()), 299 prefetch = Seq(BOPParameters()) ++ 300 (if (tp) Seq(TPParameters()) else Nil) ++ 301 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil), 302 hasCMO = p.HasCMO && site(EnableCHI), 303 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 304 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 305 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 306 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 307 )), 308 L2NBanks = banks 309 )) 310}) 311 312class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 313 case SoCParamsKey => 314 val sets = n * 1024 / banks / ways / 64 315 val tiles = site(XSTileKey) 316 val clientDirBytes = tiles.map{ t => 317 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 318 }.sum 319 up(SoCParamsKey).copy( 320 L3NBanks = banks, 321 L3CacheParamsOpt = Some(HCCacheParameters( 322 name = "L3", 323 level = 3, 324 ways = ways, 325 sets = sets, 326 inclusive = inclusive, 327 clientCaches = tiles.map{ core => 328 val l2params = core.L2CacheParamsOpt.get.toCacheParams 329 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 330 }, 331 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 332 ctrl = Some(CacheCtrl( 333 address = 0x39000000, 334 numCores = tiles.size 335 )), 336 reqField = Seq(utility.ReqSourceField()), 337 sramClkDivBy2 = true, 338 sramDepthDiv = 4, 339 tagECC = Some("secded"), 340 dataECC = Some("secded"), 341 simulation = !site(DebugOptionsKey).FPGAPlatform, 342 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 343 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 344 )), 345 OpenLLCParamsOpt = Some(OpenLLCParam( 346 name = "LLC", 347 ways = ways, 348 sets = sets, 349 banks = banks, 350 fullAddressBits = 48, 351 clientCaches = tiles.map { core => 352 val l2params = core.L2CacheParamsOpt.get 353 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 354 } 355 )) 356 ) 357}) 358 359class WithL3DebugConfig extends Config( 360 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 361) 362 363class MinimalL3DebugConfig(n: Int = 1) extends Config( 364 new WithL3DebugConfig ++ new MinimalConfig(n) 365) 366 367class DefaultL3DebugConfig(n: Int = 1) extends Config( 368 new WithL3DebugConfig ++ new BaseConfig(n) 369) 370 371class WithFuzzer extends Config((site, here, up) => { 372 case DebugOptionsKey => up(DebugOptionsKey).copy( 373 EnablePerfDebug = false, 374 ) 375 case SoCParamsKey => up(SoCParamsKey).copy( 376 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 377 enablePerf = false, 378 )), 379 ) 380 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 381 p.copy( 382 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 383 enablePerf = false, 384 )), 385 ) 386 } 387}) 388 389class MinimalAliasDebugConfig(n: Int = 1) extends Config( 390 new WithNKBL3(512, inclusive = false) ++ 391 new WithNKBL2(256, inclusive = true) ++ 392 new WithNKBL1D(128) ++ 393 new MinimalConfig(n) 394) 395 396class MediumConfig(n: Int = 1) extends Config( 397 new WithNKBL3(4096, inclusive = false, banks = 4) 398 ++ new WithNKBL2(512, inclusive = true) 399 ++ new WithNKBL1D(128) 400 ++ new BaseConfig(n) 401) 402 403class FuzzConfig(dummy: Int = 0) extends Config( 404 new WithFuzzer 405 ++ new DefaultConfig(1) 406) 407 408class DefaultConfig(n: Int = 1) extends Config( 409 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 410 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 411 ++ new WithNKBL1D(64, ways = 4) 412 ++ new BaseConfig(n) 413) 414 415class WithCHI extends Config((_, _, _) => { 416 case EnableCHI => true 417}) 418 419class KunminghuV2Config(n: Int = 1) extends Config( 420 new WithCHI 421 ++ new Config((site, here, up) => { 422 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 423 }) 424 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false) 425 ++ new WithNKBL1D(64, ways = 4) 426 ++ new DefaultConfig(n) 427) 428 429class KunminghuV2MinimalConfig(n: Int = 1) extends Config( 430 new WithCHI 431 ++ new Config((site, here, up) => { 432 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 433 }) 434 ++ new WithNKBL2(128, inclusive = true, banks = 1, tp = false) 435 ++ new WithNKBL1D(32, ways = 4) 436 ++ new MinimalConfig(n) 437) 438 439class XSNoCTopConfig(n: Int = 1) extends Config( 440 (new KunminghuV2Config(n)).alter((site, here, up) => { 441 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 442 }) 443) 444 445class XSNoCTopMinimalConfig(n: Int = 1) extends Config( 446 (new KunminghuV2MinimalConfig(n)).alter((site, here, up) => { 447 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 448 }) 449) 450 451class FpgaDefaultConfig(n: Int = 1) extends Config( 452 (new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6) 453 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 454 ++ new WithNKBL1D(64, ways = 4) 455 ++ new BaseConfig(n)).alter((site, here, up) => { 456 case DebugOptionsKey => up(DebugOptionsKey).copy( 457 AlwaysBasicDiff = false, 458 AlwaysBasicDB = false 459 ) 460 case SoCParamsKey => up(SoCParamsKey).copy( 461 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 462 sramClkDivBy2 = false, 463 )), 464 ) 465 }) 466) 467 468class FpgaDiffDefaultConfig(n: Int = 1) extends Config( 469 (new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6) 470 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 471 ++ new WithNKBL1D(64, ways = 8) 472 ++ new BaseConfig(n)).alter((site, here, up) => { 473 case DebugOptionsKey => up(DebugOptionsKey).copy( 474 AlwaysBasicDiff = true, 475 AlwaysBasicDB = false 476 ) 477 case SoCParamsKey => up(SoCParamsKey).copy( 478 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 479 sramClkDivBy2 = false, 480 )), 481 ) 482 }) 483) 484