1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import chipsalliance.rocketchip.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.MaxHartIdBits 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.exu.ExuParameters 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36 37class BaseConfig(n: Int) extends Config((site, here, up) => { 38 case XLen => 64 39 case DebugOptionsKey => DebugOptions() 40 case SoCParamsKey => SoCParameters() 41 case PMParameKey => PMParameters() 42 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 43 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 44 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 45 case JtagDTMKey => JtagDTMKey 46 case MaxHartIdBits => 2 47 case EnableJtag => true.B 48}) 49 50// Synthesizable minimal XiangShan 51// * It is still an out-of-order, super-scalaer arch 52// * L1 cache included 53// * L2 cache NOT included 54// * L3 cache included 55class MinimalConfig(n: Int = 1) extends Config( 56 new BaseConfig(n).alter((site, here, up) => { 57 case XSTileKey => up(XSTileKey).map( 58 _.copy( 59 DecodeWidth = 2, 60 RenameWidth = 2, 61 CommitWidth = 2, 62 FetchWidth = 4, 63 IssQueSize = 8, 64 NRPhyRegs = 64, 65 LoadQueueSize = 16, 66 LoadQueueNWriteBanks = 4, 67 StoreQueueSize = 12, 68 StoreQueueNWriteBanks = 4, 69 RobSize = 32, 70 FtqSize = 8, 71 IBufSize = 16, 72 StoreBufferSize = 4, 73 StoreBufferThreshold = 3, 74 dpParams = DispatchParameters( 75 IntDqSize = 12, 76 FpDqSize = 12, 77 LsDqSize = 12, 78 IntDqDeqWidth = 4, 79 FpDqDeqWidth = 4, 80 LsDqDeqWidth = 4 81 ), 82 exuParameters = ExuParameters( 83 JmpCnt = 1, 84 AluCnt = 2, 85 MulCnt = 0, 86 MduCnt = 1, 87 FmacCnt = 1, 88 FmiscCnt = 1, 89 FmiscDivSqrtCnt = 0, 90 LduCnt = 2, 91 StuCnt = 2 92 ), 93 icacheParameters = ICacheParameters( 94 nSets = 64, // 16KB ICache 95 tagECC = Some("parity"), 96 dataECC = Some("parity"), 97 replacer = Some("setplru"), 98 nMissEntries = 2, 99 nReleaseEntries = 1, 100 nProbeEntries = 2, 101 nPrefetchEntries = 2, 102 hasPrefetch = false 103 ), 104 dcacheParametersOpt = Some(DCacheParameters( 105 nSets = 64, // 32KB DCache 106 nWays = 8, 107 tagECC = Some("secded"), 108 dataECC = Some("secded"), 109 replacer = Some("setplru"), 110 nMissEntries = 4, 111 nProbeEntries = 4, 112 nReleaseEntries = 8, 113 )), 114 EnableBPD = false, // disable TAGE 115 EnableLoop = false, 116 itlbParameters = TLBParameters( 117 name = "itlb", 118 fetchi = true, 119 useDmode = false, 120 normalReplacer = Some("plru"), 121 superReplacer = Some("plru"), 122 normalNWays = 4, 123 normalNSets = 1, 124 superNWays = 2 125 ), 126 ldtlbParameters = TLBParameters( 127 name = "ldtlb", 128 normalNSets = 16, // when da or sa 129 normalNWays = 1, // when fa or sa 130 normalAssociative = "sa", 131 normalReplacer = Some("setplru"), 132 superNWays = 4, 133 normalAsVictim = true, 134 partialStaticPMP = true, 135 outsideRecvFlush = true, 136 outReplace = false 137 ), 138 sttlbParameters = TLBParameters( 139 name = "sttlb", 140 normalNSets = 16, // when da or sa 141 normalNWays = 1, // when fa or sa 142 normalAssociative = "sa", 143 normalReplacer = Some("setplru"), 144 normalAsVictim = true, 145 superNWays = 4, 146 partialStaticPMP = true, 147 outsideRecvFlush = true, 148 outReplace = false 149 ), 150 pftlbParameters = TLBParameters( 151 name = "pftlb", 152 normalNSets = 16, // when da or sa 153 normalNWays = 1, // when fa or sa 154 normalAssociative = "sa", 155 normalReplacer = Some("setplru"), 156 normalAsVictim = true, 157 superNWays = 4, 158 partialStaticPMP = true, 159 outsideRecvFlush = true, 160 outReplace = false 161 ), 162 btlbParameters = TLBParameters( 163 name = "btlb", 164 normalNSets = 1, 165 normalNWays = 8, 166 superNWays = 2 167 ), 168 l2tlbParameters = L2TLBParameters( 169 l1Size = 4, 170 l2nSets = 4, 171 l2nWays = 4, 172 l3nSets = 4, 173 l3nWays = 8, 174 spSize = 2, 175 ), 176 L2CacheParamsOpt = None, // remove L2 Cache 177 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 178 ) 179 ) 180 case SoCParamsKey => 181 val tiles = site(XSTileKey) 182 up(SoCParamsKey).copy( 183 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 184 sets = 1024, 185 inclusive = false, 186 clientCaches = tiles.map{ p => 187 CacheParameters( 188 "dcache", 189 sets = 2 * p.dcacheParametersOpt.get.nSets, 190 ways = p.dcacheParametersOpt.get.nWays + 2, 191 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets), 192 aliasBitsOpt = None 193 ) 194 }, 195 simulation = !site(DebugOptionsKey).FPGAPlatform 196 )), 197 L3NBanks = 1 198 ) 199 }) 200) 201 202// Non-synthesizable MinimalConfig, for fast simulation only 203class MinimalSimConfig(n: Int = 1) extends Config( 204 new MinimalConfig(n).alter((site, here, up) => { 205 case XSTileKey => up(XSTileKey).map(_.copy( 206 dcacheParametersOpt = None, 207 softPTW = true 208 )) 209 case SoCParamsKey => up(SoCParamsKey).copy( 210 L3CacheParamsOpt = None 211 ) 212 }) 213) 214 215class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 216 case XSTileKey => 217 val sets = n * 1024 / ways / 64 218 up(XSTileKey).map(_.copy( 219 dcacheParametersOpt = Some(DCacheParameters( 220 nSets = sets, 221 nWays = ways, 222 tagECC = Some("secded"), 223 dataECC = Some("secded"), 224 replacer = Some("setplru"), 225 nMissEntries = 16, 226 nProbeEntries = 8, 227 nReleaseEntries = 18 228 )) 229 )) 230}) 231 232class WithNKBL2 233( 234 n: Int, 235 ways: Int = 8, 236 inclusive: Boolean = true, 237 banks: Int = 1, 238 alwaysReleaseData: Boolean = false 239) extends Config((site, here, up) => { 240 case XSTileKey => 241 val upParams = up(XSTileKey) 242 val l2sets = n * 1024 / banks / ways / 64 243 upParams.map(p => p.copy( 244 L2CacheParamsOpt = Some(HCCacheParameters( 245 name = "L2", 246 level = 2, 247 ways = ways, 248 sets = l2sets, 249 inclusive = inclusive, 250 alwaysReleaseData = alwaysReleaseData, 251 clientCaches = Seq(CacheParameters( 252 "dcache", 253 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 254 ways = p.dcacheParametersOpt.get.nWays + 2, 255 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets / banks), 256 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 257 )), 258 reqField = Seq(PreferCacheField()), 259 echoField = Seq(DirtyField()), 260 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()), 261 enablePerf = true, 262 sramDepthDiv = 2, 263 tagECC = Some("secded"), 264 dataECC = Some("secded"), 265 simulation = !site(DebugOptionsKey).FPGAPlatform 266 )), 267 L2NBanks = banks 268 )) 269}) 270 271class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 272 case SoCParamsKey => 273 val sets = n * 1024 / banks / ways / 64 274 val tiles = site(XSTileKey) 275 val clientDirBytes = tiles.map{ t => 276 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 277 }.sum 278 up(SoCParamsKey).copy( 279 L3NBanks = banks, 280 L3CacheParamsOpt = Some(HCCacheParameters( 281 name = "L3", 282 level = 3, 283 ways = ways, 284 sets = sets, 285 inclusive = inclusive, 286 clientCaches = tiles.map{ core => 287 val l2params = core.L2CacheParamsOpt.get.toCacheParams 288 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 289 }, 290 enablePerf = true, 291 ctrl = Some(CacheCtrl( 292 address = 0x39000000, 293 numCores = tiles.size 294 )), 295 sramClkDivBy2 = true, 296 sramDepthDiv = 4, 297 tagECC = Some("secded"), 298 dataECC = Some("secded"), 299 simulation = !site(DebugOptionsKey).FPGAPlatform 300 )) 301 ) 302}) 303 304class WithL3DebugConfig extends Config( 305 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 306) 307 308class MinimalL3DebugConfig(n: Int = 1) extends Config( 309 new WithL3DebugConfig ++ new MinimalConfig(n) 310) 311 312class DefaultL3DebugConfig(n: Int = 1) extends Config( 313 new WithL3DebugConfig ++ new BaseConfig(n) 314) 315 316class MinimalAliasDebugConfig(n: Int = 1) extends Config( 317 new WithNKBL3(512, inclusive = false) ++ 318 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 319 new WithNKBL1D(128) ++ 320 new MinimalConfig(n) 321) 322 323class MediumConfig(n: Int = 1) extends Config( 324 new WithNKBL3(4096, inclusive = false, banks = 4) 325 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 326 ++ new WithNKBL1D(128) 327 ++ new BaseConfig(n) 328) 329 330class DefaultConfig(n: Int = 1) extends Config( 331 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 332 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 333 ++ new WithNKBL1D(128) 334 ++ new BaseConfig(n) 335) 336