1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import chipsalliance.rocketchip.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.MaxHartIdBits 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.exu.ExuParameters 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36import coupledL2._ 37 38class BaseConfig(n: Int) extends Config((site, here, up) => { 39 case XLen => 64 40 case DebugOptionsKey => DebugOptions() 41 case SoCParamsKey => SoCParameters() 42 case PMParameKey => PMParameters() 43 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 44 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 45 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 46 case JtagDTMKey => JtagDTMKey 47 case MaxHartIdBits => 2 48 case EnableJtag => true.B 49}) 50 51// Synthesizable minimal XiangShan 52// * It is still an out-of-order, super-scalaer arch 53// * L1 cache included 54// * L2 cache NOT included 55// * L3 cache included 56class MinimalConfig(n: Int = 1) extends Config( 57 new BaseConfig(n).alter((site, here, up) => { 58 case XSTileKey => up(XSTileKey).map( 59 _.copy( 60 DecodeWidth = 2, 61 RenameWidth = 2, 62 CommitWidth = 2, 63 FetchWidth = 4, 64 IssQueSize = 8, 65 NRPhyRegs = 64, 66 VirtualLoadQueueSize = 16, 67 LoadQueueRARSize = 16, 68 LoadQueueRAWSize = 12, 69 LoadQueueReplaySize = 8, 70 LoadUncacheBufferSize = 8, 71 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 72 RollbackGroupSize = 8, 73 StoreQueueSize = 12, 74 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 75 StoreQueueForwardWithMask = true, 76 RobSize = 32, 77 FtqSize = 8, 78 IBufSize = 16, 79 StoreBufferSize = 4, 80 StoreBufferThreshold = 3, 81 dpParams = DispatchParameters( 82 IntDqSize = 12, 83 FpDqSize = 12, 84 LsDqSize = 12, 85 IntDqDeqWidth = 4, 86 FpDqDeqWidth = 4, 87 LsDqDeqWidth = 4 88 ), 89 exuParameters = ExuParameters( 90 JmpCnt = 1, 91 AluCnt = 2, 92 MulCnt = 0, 93 MduCnt = 1, 94 FmacCnt = 1, 95 FmiscCnt = 1, 96 FmiscDivSqrtCnt = 0, 97 LduCnt = 2, 98 StuCnt = 2 99 ), 100 icacheParameters = ICacheParameters( 101 nSets = 64, // 16KB ICache 102 tagECC = Some("parity"), 103 dataECC = Some("parity"), 104 replacer = Some("setplru"), 105 nMissEntries = 2, 106 nReleaseEntries = 1, 107 nProbeEntries = 2, 108 nPrefetchEntries = 2, 109 nPrefBufferEntries = 32, 110 hasPrefetch = true 111 ), 112 dcacheParametersOpt = Some(DCacheParameters( 113 nSets = 64, // 32KB DCache 114 nWays = 8, 115 tagECC = Some("secded"), 116 dataECC = Some("secded"), 117 replacer = Some("setplru"), 118 nMissEntries = 4, 119 nProbeEntries = 4, 120 nReleaseEntries = 8, 121 nMaxPrefetchEntry = 2, 122 )), 123 EnableBPD = false, // disable TAGE 124 EnableLoop = false, 125 itlbParameters = TLBParameters( 126 name = "itlb", 127 fetchi = true, 128 useDmode = false, 129 NWays = 4, 130 ), 131 ldtlbParameters = TLBParameters( 132 name = "ldtlb", 133 NWays = 4, 134 partialStaticPMP = true, 135 outsideRecvFlush = true, 136 outReplace = false 137 ), 138 sttlbParameters = TLBParameters( 139 name = "sttlb", 140 NWays = 4, 141 partialStaticPMP = true, 142 outsideRecvFlush = true, 143 outReplace = false 144 ), 145 pftlbParameters = TLBParameters( 146 name = "pftlb", 147 NWays = 4, 148 partialStaticPMP = true, 149 outsideRecvFlush = true, 150 outReplace = false 151 ), 152 btlbParameters = TLBParameters( 153 name = "btlb", 154 NWays = 4, 155 ), 156 l2tlbParameters = L2TLBParameters( 157 l1Size = 4, 158 l2nSets = 4, 159 l2nWays = 4, 160 l3nSets = 4, 161 l3nWays = 8, 162 spSize = 2, 163 ), 164 L2CacheParamsOpt = Some(L2Param( 165 name = "L2", 166 ways = 8, 167 sets = 128, 168 echoField = Seq(huancun.DirtyField()), 169 prefetch = None 170 )), 171 L2NBanks = 2, 172 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 173 ) 174 ) 175 case SoCParamsKey => 176 val tiles = site(XSTileKey) 177 up(SoCParamsKey).copy( 178 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 179 sets = 1024, 180 inclusive = false, 181 clientCaches = tiles.map{ core => 182 val clientDirBytes = tiles.map{ t => 183 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 184 }.sum 185 val l2params = core.L2CacheParamsOpt.get.toCacheParams 186 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 187 }, 188 simulation = !site(DebugOptionsKey).FPGAPlatform, 189 prefetch = None 190 )), 191 L3NBanks = 1 192 ) 193 }) 194) 195 196// Non-synthesizable MinimalConfig, for fast simulation only 197class MinimalSimConfig(n: Int = 1) extends Config( 198 new MinimalConfig(n).alter((site, here, up) => { 199 case XSTileKey => up(XSTileKey).map(_.copy( 200 dcacheParametersOpt = None, 201 softPTW = true 202 )) 203 case SoCParamsKey => up(SoCParamsKey).copy( 204 L3CacheParamsOpt = None 205 ) 206 }) 207) 208 209class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 210 case XSTileKey => 211 val sets = n * 1024 / ways / 64 212 up(XSTileKey).map(_.copy( 213 dcacheParametersOpt = Some(DCacheParameters( 214 nSets = sets, 215 nWays = ways, 216 tagECC = Some("secded"), 217 dataECC = Some("secded"), 218 replacer = Some("setplru"), 219 nMissEntries = 16, 220 nProbeEntries = 8, 221 nReleaseEntries = 18, 222 nMaxPrefetchEntry = 6, 223 )) 224 )) 225}) 226 227class WithNKBL2 228( 229 n: Int, 230 ways: Int = 8, 231 inclusive: Boolean = true, 232 banks: Int = 1 233) extends Config((site, here, up) => { 234 case XSTileKey => 235 val upParams = up(XSTileKey) 236 val l2sets = n * 1024 / banks / ways / 64 237 upParams.map(p => p.copy( 238 L2CacheParamsOpt = Some(L2Param( 239 name = "L2", 240 ways = ways, 241 sets = l2sets, 242 clientCaches = Seq(L1Param( 243 "dcache", 244 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 245 ways = p.dcacheParametersOpt.get.nWays + 2, 246 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 247 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)) 248 )), 249 reqField = Seq(utility.ReqSourceField()), 250 echoField = Seq(huancun.DirtyField()), 251 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 252 )), 253 L2NBanks = banks 254 )) 255}) 256 257class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 258 case SoCParamsKey => 259 val sets = n * 1024 / banks / ways / 64 260 val tiles = site(XSTileKey) 261 val clientDirBytes = tiles.map{ t => 262 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 263 }.sum 264 up(SoCParamsKey).copy( 265 L3NBanks = banks, 266 L3CacheParamsOpt = Some(HCCacheParameters( 267 name = "L3", 268 level = 3, 269 ways = ways, 270 sets = sets, 271 inclusive = inclusive, 272 clientCaches = tiles.map{ core => 273 val l2params = core.L2CacheParamsOpt.get.toCacheParams 274 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 275 }, 276 enablePerf = true, 277 ctrl = Some(CacheCtrl( 278 address = 0x39000000, 279 numCores = tiles.size 280 )), 281 reqField = Seq(utility.ReqSourceField()), 282 sramClkDivBy2 = true, 283 sramDepthDiv = 4, 284 tagECC = Some("secded"), 285 dataECC = Some("secded"), 286 simulation = !site(DebugOptionsKey).FPGAPlatform, 287 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()) 288 )) 289 ) 290}) 291 292class WithL3DebugConfig extends Config( 293 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 294) 295 296class MinimalL3DebugConfig(n: Int = 1) extends Config( 297 new WithL3DebugConfig ++ new MinimalConfig(n) 298) 299 300class DefaultL3DebugConfig(n: Int = 1) extends Config( 301 new WithL3DebugConfig ++ new BaseConfig(n) 302) 303 304class WithFuzzer extends Config((site, here, up) => { 305 case DebugOptionsKey => up(DebugOptionsKey).copy( 306 EnablePerfDebug = false, 307 ) 308 case SoCParamsKey => up(SoCParamsKey).copy( 309 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 310 enablePerf = false, 311 )), 312 ) 313 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 314 p.copy( 315 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 316 enablePerf = false, 317 )), 318 ) 319 } 320}) 321 322class MinimalAliasDebugConfig(n: Int = 1) extends Config( 323 new WithNKBL3(512, inclusive = false) ++ 324 new WithNKBL2(256, inclusive = false) ++ 325 new WithNKBL1D(128) ++ 326 new MinimalConfig(n) 327) 328 329class MediumConfig(n: Int = 1) extends Config( 330 new WithNKBL3(4096, inclusive = false, banks = 4) 331 ++ new WithNKBL2(512, inclusive = false) 332 ++ new WithNKBL1D(128) 333 ++ new BaseConfig(n) 334) 335 336class FuzzConfig(dummy: Int = 0) extends Config( 337 new WithFuzzer 338 ++ new DefaultConfig(1) 339) 340 341class DefaultConfig(n: Int = 1) extends Config( 342 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 343 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4) 344 ++ new WithNKBL1D(128) 345 ++ new BaseConfig(n) 346) 347