1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import freechips.rocketchip.devices.debug._ 27import freechips.rocketchip.tile.MaxHartIdBits 28import sifive.blocks.inclusivecache.{InclusiveCache, InclusiveCacheMicroParameters, CacheParameters} 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.backend.exu.ExuParameters 31import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 32import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 33import device.{XSDebugModuleParams, EnableJtag} 34 35class DefaultConfig(n: Int) extends Config((site, here, up) => { 36 case XLen => 64 37 case DebugOptionsKey => DebugOptions() 38 case SoCParamsKey => SoCParameters( 39 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 40 ) 41 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 42 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 43 case JtagDTMKey => JtagDTMKey 44 case MaxHartIdBits => 2 45 case EnableJtag => false.B 46}) 47 48// Synthesizable minimal XiangShan 49// * It is still an out-of-order, super-scalaer arch 50// * L1 cache included 51// * L2 cache NOT included 52// * L3 cache included 53class MinimalConfig(n: Int = 1) extends Config( 54 new DefaultConfig(n).alter((site, here, up) => { 55 case SoCParamsKey => up(SoCParamsKey).copy( 56 cores = up(SoCParamsKey).cores.map(_.copy( 57 DecodeWidth = 2, 58 RenameWidth = 2, 59 FetchWidth = 4, 60 IssQueSize = 8, 61 NRPhyRegs = 64, 62 LoadQueueSize = 16, 63 StoreQueueSize = 12, 64 RoqSize = 32, 65 BrqSize = 8, 66 FtqSize = 8, 67 IBufSize = 16, 68 StoreBufferSize = 4, 69 StoreBufferThreshold = 3, 70 dpParams = DispatchParameters( 71 IntDqSize = 12, 72 FpDqSize = 12, 73 LsDqSize = 12, 74 IntDqDeqWidth = 4, 75 FpDqDeqWidth = 4, 76 LsDqDeqWidth = 4 77 ), 78 exuParameters = ExuParameters( 79 JmpCnt = 1, 80 AluCnt = 2, 81 MulCnt = 0, 82 MduCnt = 1, 83 FmacCnt = 1, 84 FmiscCnt = 1, 85 FmiscDivSqrtCnt = 0, 86 LduCnt = 2, 87 StuCnt = 2 88 ), 89 icacheParameters = ICacheParameters( 90 nSets = 64, // 16KB ICache 91 tagECC = Some("parity"), 92 dataECC = Some("parity"), 93 replacer = Some("setplru"), 94 nMissEntries = 2 95 ), 96 dcacheParameters = DCacheParameters( 97 nSets = 64, // 32KB DCache 98 nWays = 8, 99 tagECC = Some("secded"), 100 dataECC = Some("secded"), 101 replacer = Some("setplru"), 102 nMissEntries = 4, 103 nProbeEntries = 4, 104 nReleaseEntries = 4, 105 nStoreReplayEntries = 4, 106 ), 107 EnableBPD = false, // disable TAGE 108 EnableLoop = false, 109 TlbEntrySize = 2, 110 TlbSPEntrySize = 2, 111 BTlbEntrySize = 8, 112 PtwL1EntrySize = 2, 113 PtwL2EntrySize = 64, 114 PtwL3EntrySize = 128, 115 PtwSPEntrySize = 2, 116 useFakeL2Cache = true, // disable L2 Cache 117 )), 118 L3Size = 256 * 1024, // 256KB L3 Cache 119 ) 120 }) 121) 122 123// Non-synthesizable MinimalConfig, for fast simulation only 124class MinimalSimConfig(n: Int = 1) extends Config( 125 new MinimalConfig(n).alter((site, here, up) => { 126 case SoCParamsKey => up(SoCParamsKey).copy( 127 cores = up(SoCParamsKey).cores.map(_.copy( 128 useFakeDCache = true, 129 useFakePTW = true, 130 useFakeL1plusCache = true, 131 )), 132 useFakeL3Cache = true 133 ) 134 }) 135) 136