1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import xiangshan.frontend.icache.ICacheParameters 43 44class BaseConfig(n: Int) extends Config((site, here, up) => { 45 case XLen => 64 46 case DebugOptionsKey => DebugOptions() 47 case SoCParamsKey => SoCParameters() 48 case PMParameKey => PMParameters() 49 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 50 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 51 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 52 case JtagDTMKey => JtagDTMKey 53 case MaxHartIdBits => log2Up(n) 54 case EnableJtag => true.B 55}) 56 57// Synthesizable minimal XiangShan 58// * It is still an out-of-order, super-scalaer arch 59// * L1 cache included 60// * L2 cache NOT included 61// * L3 cache included 62class MinimalConfig(n: Int = 1) extends Config( 63 new BaseConfig(n).alter((site, here, up) => { 64 case XSTileKey => up(XSTileKey).map( 65 p => p.copy( 66 DecodeWidth = 6, 67 RenameWidth = 6, 68 RobCommitWidth = 8, 69 FetchWidth = 4, 70 VirtualLoadQueueSize = 24, 71 LoadQueueRARSize = 16, 72 LoadQueueRAWSize = 12, 73 LoadQueueReplaySize = 24, 74 LoadUncacheBufferSize = 8, 75 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 76 RollbackGroupSize = 8, 77 StoreQueueSize = 20, 78 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 79 StoreQueueForwardWithMask = true, 80 RobSize = 48, 81 RabSize = 96, 82 FtqSize = 8, 83 IBufSize = 24, 84 IBufNBank = 6, 85 StoreBufferSize = 4, 86 StoreBufferThreshold = 3, 87 IssueQueueSize = 8, 88 IssueQueueCompEntrySize = 4, 89 dpParams = DispatchParameters( 90 IntDqSize = 12, 91 FpDqSize = 12, 92 LsDqSize = 12, 93 IntDqDeqWidth = 8, 94 FpDqDeqWidth = 6, 95 VecDqDeqWidth = 6, 96 LsDqDeqWidth = 6 97 ), 98 intPreg = IntPregParams( 99 numEntries = 64, 100 numRead = None, 101 numWrite = None, 102 ), 103 vfPreg = VfPregParams( 104 numEntries = 160, 105 numRead = None, 106 numWrite = None, 107 ), 108 icacheParameters = ICacheParameters( 109 nSets = 64, // 16KB ICache 110 tagECC = Some("parity"), 111 dataECC = Some("parity"), 112 replacer = Some("setplru"), 113 nMissEntries = 2, 114 nReleaseEntries = 1, 115 nProbeEntries = 2, 116 // fdip 117 enableICachePrefetch = true, 118 prefetchToL1 = false, 119 ), 120 dcacheParametersOpt = Some(DCacheParameters( 121 nSets = 64, // 32KB DCache 122 nWays = 8, 123 tagECC = Some("secded"), 124 dataECC = Some("secded"), 125 replacer = Some("setplru"), 126 nMissEntries = 4, 127 nProbeEntries = 4, 128 nReleaseEntries = 8, 129 nMaxPrefetchEntry = 2, 130 )), 131 EnableBPD = false, // disable TAGE 132 EnableLoop = false, 133 itlbParameters = TLBParameters( 134 name = "itlb", 135 fetchi = true, 136 useDmode = false, 137 NWays = 4, 138 ), 139 ldtlbParameters = TLBParameters( 140 name = "ldtlb", 141 NWays = 4, 142 partialStaticPMP = true, 143 outsideRecvFlush = true, 144 outReplace = false 145 ), 146 sttlbParameters = TLBParameters( 147 name = "sttlb", 148 NWays = 4, 149 partialStaticPMP = true, 150 outsideRecvFlush = true, 151 outReplace = false 152 ), 153 hytlbParameters = TLBParameters( 154 name = "hytlb", 155 NWays = 4, 156 partialStaticPMP = true, 157 outsideRecvFlush = true, 158 outReplace = false 159 ), 160 pftlbParameters = TLBParameters( 161 name = "pftlb", 162 NWays = 4, 163 partialStaticPMP = true, 164 outsideRecvFlush = true, 165 outReplace = false 166 ), 167 btlbParameters = TLBParameters( 168 name = "btlb", 169 NWays = 4, 170 ), 171 l2tlbParameters = L2TLBParameters( 172 l1Size = 4, 173 l2nSets = 4, 174 l2nWays = 4, 175 l3nSets = 4, 176 l3nWays = 8, 177 spSize = 2, 178 ), 179 L2CacheParamsOpt = Some(L2Param( 180 name = "L2", 181 ways = 8, 182 sets = 128, 183 echoField = Seq(huancun.DirtyField()), 184 prefetch = None, 185 clientCaches = Seq(L1Param( 186 "dcache", 187 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 188 )), 189 ) 190 ), 191 L2NBanks = 2, 192 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 193 ) 194 ) 195 case SoCParamsKey => 196 val tiles = site(XSTileKey) 197 up(SoCParamsKey).copy( 198 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 199 sets = 1024, 200 inclusive = false, 201 clientCaches = tiles.map{ core => 202 val clientDirBytes = tiles.map{ t => 203 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 204 }.sum 205 val l2params = core.L2CacheParamsOpt.get.toCacheParams 206 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 207 }, 208 simulation = !site(DebugOptionsKey).FPGAPlatform, 209 prefetch = None 210 )), 211 L3NBanks = 1 212 ) 213 }) 214) 215 216// Non-synthesizable MinimalConfig, for fast simulation only 217class MinimalSimConfig(n: Int = 1) extends Config( 218 new MinimalConfig(n).alter((site, here, up) => { 219 case XSTileKey => up(XSTileKey).map(_.copy( 220 dcacheParametersOpt = None, 221 softPTW = true 222 )) 223 case SoCParamsKey => up(SoCParamsKey).copy( 224 L3CacheParamsOpt = None 225 ) 226 }) 227) 228 229class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 230 case XSTileKey => 231 val sets = n * 1024 / ways / 64 232 up(XSTileKey).map(_.copy( 233 dcacheParametersOpt = Some(DCacheParameters( 234 nSets = sets, 235 nWays = ways, 236 tagECC = Some("secded"), 237 dataECC = Some("secded"), 238 replacer = Some("setplru"), 239 nMissEntries = 16, 240 nProbeEntries = 8, 241 nReleaseEntries = 18, 242 nMaxPrefetchEntry = 6, 243 )) 244 )) 245}) 246 247class WithNKBL2 248( 249 n: Int, 250 ways: Int = 8, 251 inclusive: Boolean = true, 252 banks: Int = 1 253) extends Config((site, here, up) => { 254 case XSTileKey => 255 require(inclusive, "L2 must be inclusive") 256 val upParams = up(XSTileKey) 257 val l2sets = n * 1024 / banks / ways / 64 258 upParams.map(p => p.copy( 259 L2CacheParamsOpt = Some(L2Param( 260 name = "L2", 261 ways = ways, 262 sets = l2sets, 263 clientCaches = Seq(L1Param( 264 "dcache", 265 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 266 ways = p.dcacheParametersOpt.get.nWays + 2, 267 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 268 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)), 269 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 270 )), 271 reqField = Seq(utility.ReqSourceField()), 272 echoField = Seq(huancun.DirtyField()), 273 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()), 274 enablePerf = !site(DebugOptionsKey).FPGAPlatform, 275 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 276 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 277 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 278 )), 279 L2NBanks = banks 280 )) 281}) 282 283class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 284 case SoCParamsKey => 285 val sets = n * 1024 / banks / ways / 64 286 val tiles = site(XSTileKey) 287 val clientDirBytes = tiles.map{ t => 288 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 289 }.sum 290 up(SoCParamsKey).copy( 291 L3NBanks = banks, 292 L3CacheParamsOpt = Some(HCCacheParameters( 293 name = "L3", 294 level = 3, 295 ways = ways, 296 sets = sets, 297 inclusive = inclusive, 298 clientCaches = tiles.map{ core => 299 val l2params = core.L2CacheParamsOpt.get.toCacheParams 300 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 301 }, 302 enablePerf = true, 303 ctrl = Some(CacheCtrl( 304 address = 0x39000000, 305 numCores = tiles.size 306 )), 307 reqField = Seq(utility.ReqSourceField()), 308 sramClkDivBy2 = true, 309 sramDepthDiv = 4, 310 tagECC = Some("secded"), 311 dataECC = Some("secded"), 312 simulation = !site(DebugOptionsKey).FPGAPlatform, 313 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 314 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 315 )) 316 ) 317}) 318 319class WithL3DebugConfig extends Config( 320 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 321) 322 323class MinimalL3DebugConfig(n: Int = 1) extends Config( 324 new WithL3DebugConfig ++ new MinimalConfig(n) 325) 326 327class DefaultL3DebugConfig(n: Int = 1) extends Config( 328 new WithL3DebugConfig ++ new BaseConfig(n) 329) 330 331class WithFuzzer extends Config((site, here, up) => { 332 case DebugOptionsKey => up(DebugOptionsKey).copy( 333 EnablePerfDebug = false, 334 ) 335 case SoCParamsKey => up(SoCParamsKey).copy( 336 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 337 enablePerf = false, 338 )), 339 ) 340 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 341 p.copy( 342 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 343 enablePerf = false, 344 )), 345 ) 346 } 347}) 348 349class MinimalAliasDebugConfig(n: Int = 1) extends Config( 350 new WithNKBL3(512, inclusive = false) ++ 351 new WithNKBL2(256, inclusive = true) ++ 352 new WithNKBL1D(128) ++ 353 new MinimalConfig(n) 354) 355 356class MediumConfig(n: Int = 1) extends Config( 357 new WithNKBL3(4096, inclusive = false, banks = 4) 358 ++ new WithNKBL2(512, inclusive = true) 359 ++ new WithNKBL1D(128) 360 ++ new BaseConfig(n) 361) 362 363class FuzzConfig(dummy: Int = 0) extends Config( 364 new WithFuzzer 365 ++ new DefaultConfig(1) 366) 367 368class DefaultConfig(n: Int = 1) extends Config( 369 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 370 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 371 ++ new WithNKBL1D(64, ways = 8) 372 ++ new BaseConfig(n) 373) 374