1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import xiangshan.frontend.icache.ICacheParameters 27import freechips.rocketchip.devices.debug._ 28import freechips.rocketchip.tile.MaxHartIdBits 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.backend.exu.ExuParameters 31import xiangshan.cache.DCacheParameters 32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 33import device.{EnableJtag, XSDebugModuleParams} 34import huancun._ 35 36class BaseConfig(n: Int) extends Config((site, here, up) => { 37 case XLen => 64 38 case DebugOptionsKey => DebugOptions() 39 case SoCParamsKey => SoCParameters() 40 case PMParameKey => PMParameters() 41 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 42 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 43 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 44 case JtagDTMKey => JtagDTMKey 45 case MaxHartIdBits => 2 46 case EnableJtag => true.B 47}) 48 49// Synthesizable minimal XiangShan 50// * It is still an out-of-order, super-scalaer arch 51// * L1 cache included 52// * L2 cache NOT included 53// * L3 cache included 54class MinimalConfig(n: Int = 1) extends Config( 55 new BaseConfig(n).alter((site, here, up) => { 56 case XSTileKey => up(XSTileKey).map( 57 _.copy( 58 DecodeWidth = 2, 59 RenameWidth = 2, 60 CommitWidth = 2, 61 FetchWidth = 4, 62 IssQueSize = 8, 63 NRPhyRegs = 96, 64 IntPhyRegs = 96, 65 VfPhyRegs = 96, 66 LoadQueueSize = 16, 67 LoadQueueNWriteBanks = 4, 68 StoreQueueSize = 12, 69 StoreQueueNWriteBanks = 4, 70 RobSize = 32, 71 FtqSize = 8, 72 IBufSize = 16, 73 StoreBufferSize = 4, 74 StoreBufferThreshold = 3, 75 dpParams = DispatchParameters( 76 IntDqSize = 12, 77 FpDqSize = 12, 78 LsDqSize = 12, 79 IntDqDeqWidth = 4, 80 FpDqDeqWidth = 4, 81 LsDqDeqWidth = 4 82 ), 83 exuParameters = ExuParameters( 84 JmpCnt = 1, 85 AluCnt = 2, 86 MulCnt = 0, 87 MduCnt = 1, 88 FmacCnt = 1, 89 FmiscCnt = 1, 90 FmiscDivSqrtCnt = 0, 91 LduCnt = 2, 92 StuCnt = 2 93 ), 94 icacheParameters = ICacheParameters( 95 nSets = 64, // 16KB ICache 96 tagECC = Some("parity"), 97 dataECC = Some("parity"), 98 replacer = Some("setplru"), 99 nMissEntries = 2, 100 nReleaseEntries = 1, 101 nProbeEntries = 2, 102 nPrefetchEntries = 2, 103 hasPrefetch = false 104 ), 105 dcacheParametersOpt = Some(DCacheParameters( 106 nSets = 64, // 32KB DCache 107 nWays = 8, 108 tagECC = Some("secded"), 109 dataECC = Some("secded"), 110 replacer = Some("setplru"), 111 nMissEntries = 4, 112 nProbeEntries = 4, 113 nReleaseEntries = 8, 114 )), 115 EnableBPD = false, // disable TAGE 116 EnableLoop = false, 117 itlbParameters = TLBParameters( 118 name = "itlb", 119 fetchi = true, 120 useDmode = false, 121 normalReplacer = Some("plru"), 122 superReplacer = Some("plru"), 123 normalNWays = 4, 124 normalNSets = 1, 125 superNWays = 2 126 ), 127 ldtlbParameters = TLBParameters( 128 name = "ldtlb", 129 normalNSets = 16, // when da or sa 130 normalNWays = 1, // when fa or sa 131 normalAssociative = "sa", 132 normalReplacer = Some("setplru"), 133 superNWays = 4, 134 normalAsVictim = true, 135 partialStaticPMP = true, 136 outsideRecvFlush = true, 137 outReplace = false 138 ), 139 sttlbParameters = TLBParameters( 140 name = "sttlb", 141 normalNSets = 16, // when da or sa 142 normalNWays = 1, // when fa or sa 143 normalAssociative = "sa", 144 normalReplacer = Some("setplru"), 145 normalAsVictim = true, 146 superNWays = 4, 147 partialStaticPMP = true, 148 outsideRecvFlush = true, 149 outReplace = false 150 ), 151 btlbParameters = TLBParameters( 152 name = "btlb", 153 normalNSets = 1, 154 normalNWays = 8, 155 superNWays = 2 156 ), 157 l2tlbParameters = L2TLBParameters( 158 l1Size = 4, 159 l2nSets = 4, 160 l2nWays = 4, 161 l3nSets = 4, 162 l3nWays = 8, 163 spSize = 2, 164 ), 165 L2CacheParamsOpt = None // remove L2 Cache 166 ) 167 ) 168 case SoCParamsKey => 169 val tiles = site(XSTileKey) 170 up(SoCParamsKey).copy( 171 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 172 sets = 1024, 173 inclusive = false, 174 clientCaches = tiles.map{ p => 175 CacheParameters( 176 "dcache", 177 sets = 2 * p.dcacheParametersOpt.get.nSets, 178 ways = p.dcacheParametersOpt.get.nWays + 2, 179 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets), 180 aliasBitsOpt = None 181 ) 182 }, 183 simulation = !site(DebugOptionsKey).FPGAPlatform 184 )), 185 L3NBanks = 1 186 ) 187 }) 188) 189 190// Non-synthesizable MinimalConfig, for fast simulation only 191class MinimalSimConfig(n: Int = 1) extends Config( 192 new MinimalConfig(n).alter((site, here, up) => { 193 case XSTileKey => up(XSTileKey).map(_.copy( 194 dcacheParametersOpt = None, 195 softPTW = true 196 )) 197 case SoCParamsKey => up(SoCParamsKey).copy( 198 L3CacheParamsOpt = None 199 ) 200 }) 201) 202 203class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 204 case XSTileKey => 205 val sets = n * 1024 / ways / 64 206 up(XSTileKey).map(_.copy( 207 dcacheParametersOpt = Some(DCacheParameters( 208 nSets = sets, 209 nWays = ways, 210 tagECC = Some("secded"), 211 dataECC = Some("secded"), 212 replacer = Some("setplru"), 213 nMissEntries = 16, 214 nProbeEntries = 8, 215 nReleaseEntries = 18 216 )) 217 )) 218}) 219 220class WithNKBL2 221( 222 n: Int, 223 ways: Int = 8, 224 inclusive: Boolean = true, 225 banks: Int = 1, 226 alwaysReleaseData: Boolean = false 227) extends Config((site, here, up) => { 228 case XSTileKey => 229 val upParams = up(XSTileKey) 230 val l2sets = n * 1024 / banks / ways / 64 231 upParams.map(p => p.copy( 232 L2CacheParamsOpt = Some(HCCacheParameters( 233 name = "L2", 234 level = 2, 235 ways = ways, 236 sets = l2sets, 237 inclusive = inclusive, 238 alwaysReleaseData = alwaysReleaseData, 239 clientCaches = Seq(CacheParameters( 240 "dcache", 241 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 242 ways = p.dcacheParametersOpt.get.nWays + 2, 243 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets / banks), 244 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 245 )), 246 reqField = Seq(PreferCacheField()), 247 echoField = Seq(DirtyField()), 248 prefetch = Some(huancun.prefetch.BOPParameters()), 249 enablePerf = true, 250 sramDepthDiv = 2, 251 tagECC = Some("secded"), 252 dataECC = Some("secded"), 253 simulation = !site(DebugOptionsKey).FPGAPlatform 254 )), 255 L2NBanks = banks 256 )) 257}) 258 259class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 260 case SoCParamsKey => 261 val sets = n * 1024 / banks / ways / 64 262 val tiles = site(XSTileKey) 263 val clientDirBytes = tiles.map{ t => 264 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 265 }.sum 266 up(SoCParamsKey).copy( 267 L3NBanks = banks, 268 L3CacheParamsOpt = Some(HCCacheParameters( 269 name = "L3", 270 level = 3, 271 ways = ways, 272 sets = sets, 273 inclusive = inclusive, 274 clientCaches = tiles.map{ core => 275 val l2params = core.L2CacheParamsOpt.get.toCacheParams 276 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 277 }, 278 enablePerf = true, 279 ctrl = Some(CacheCtrl( 280 address = 0x39000000, 281 numCores = tiles.size 282 )), 283 sramClkDivBy2 = true, 284 sramDepthDiv = 4, 285 tagECC = Some("secded"), 286 dataECC = Some("secded"), 287 simulation = !site(DebugOptionsKey).FPGAPlatform 288 )) 289 ) 290}) 291 292class WithL3DebugConfig extends Config( 293 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 294) 295 296class MinimalL3DebugConfig(n: Int = 1) extends Config( 297 new WithL3DebugConfig ++ new MinimalConfig(n) 298) 299 300class DefaultL3DebugConfig(n: Int = 1) extends Config( 301 new WithL3DebugConfig ++ new BaseConfig(n) 302) 303 304class MinimalAliasDebugConfig(n: Int = 1) extends Config( 305 new WithNKBL3(512, inclusive = false) ++ 306 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 307 new WithNKBL1D(128) ++ 308 new MinimalConfig(n) 309) 310 311class MediumConfig(n: Int = 1) extends Config( 312 new WithNKBL3(4096, inclusive = false, banks = 4) 313 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 314 ++ new WithNKBL1D(128) 315 ++ new BaseConfig(n) 316) 317 318class DefaultConfig(n: Int = 1) extends Config( 319 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 320 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 321 ++ new WithNKBL1D(128) 322 ++ new BaseConfig(n) 323) 324