1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import openLLC.{OpenLLCParam} 35import freechips.rocketchip.diplomacy._ 36import xiangshan._ 37import xiangshan.backend.dispatch.DispatchParameters 38import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 39import xiangshan.cache.DCacheParameters 40import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 41import device.{EnableJtag, XSDebugModuleParams} 42import huancun._ 43import coupledL2._ 44import coupledL2.prefetch._ 45import xiangshan.frontend.icache.ICacheParameters 46 47class BaseConfig(n: Int) extends Config((site, here, up) => { 48 case XLen => 64 49 case DebugOptionsKey => DebugOptions() 50 case SoCParamsKey => SoCParameters() 51 case PMParameKey => PMParameters() 52 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 53 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 54 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 55 case JtagDTMKey => JtagDTMKey 56 case MaxHartIdBits => log2Up(n) max 6 57 case EnableJtag => true.B 58}) 59 60// Synthesizable minimal XiangShan 61// * It is still an out-of-order, super-scalaer arch 62// * L1 cache included 63// * L2 cache NOT included 64// * L3 cache included 65class MinimalConfig(n: Int = 1) extends Config( 66 new BaseConfig(n).alter((site, here, up) => { 67 case XSTileKey => up(XSTileKey).map( 68 p => p.copy( 69 DecodeWidth = 6, 70 RenameWidth = 6, 71 RobCommitWidth = 8, 72 FetchWidth = 4, 73 VirtualLoadQueueSize = 24, 74 LoadQueueRARSize = 24, 75 LoadQueueRAWSize = 12, 76 LoadQueueReplaySize = 24, 77 LoadUncacheBufferSize = 8, 78 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 79 RollbackGroupSize = 8, 80 StoreQueueSize = 20, 81 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 82 StoreQueueForwardWithMask = true, 83 // ============ VLSU ============ 84 VlMergeBufferSize = 16, 85 VsMergeBufferSize = 8, 86 UopWritebackWidth = 2, 87 // ============================== 88 RobSize = 48, 89 RabSize = 96, 90 FtqSize = 8, 91 IBufSize = 24, 92 IBufNBank = 6, 93 StoreBufferSize = 4, 94 StoreBufferThreshold = 3, 95 IssueQueueSize = 10, 96 IssueQueueCompEntrySize = 4, 97 dpParams = DispatchParameters( 98 IntDqSize = 12, 99 FpDqSize = 12, 100 LsDqSize = 12, 101 IntDqDeqWidth = 8, 102 FpDqDeqWidth = 6, 103 VecDqDeqWidth = 6, 104 LsDqDeqWidth = 6 105 ), 106 intPreg = IntPregParams( 107 numEntries = 64, 108 numRead = None, 109 numWrite = None, 110 ), 111 vfPreg = VfPregParams( 112 numEntries = 160, 113 numRead = None, 114 numWrite = None, 115 ), 116 icacheParameters = ICacheParameters( 117 nSets = 64, // 16KB ICache 118 tagECC = Some("parity"), 119 dataECC = Some("parity"), 120 replacer = Some("setplru"), 121 cacheCtrlAddressOpt = Some(AddressSet(0x38022080, 0x7f)), 122 ), 123 dcacheParametersOpt = Some(DCacheParameters( 124 nSets = 64, // 32KB DCache 125 nWays = 8, 126 tagECC = Some("secded"), 127 dataECC = Some("secded"), 128 replacer = Some("setplru"), 129 nMissEntries = 4, 130 nProbeEntries = 4, 131 nReleaseEntries = 8, 132 nMaxPrefetchEntry = 2, 133 enableTagEcc = true, 134 enableDataEcc = true, 135 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 136 )), 137 // ============ BPU =============== 138 EnableLoop = false, 139 EnableGHistDiff = false, 140 FtbSize = 256, 141 FtbWays = 2, 142 RasSize = 8, 143 RasSpecSize = 16, 144 TageTableInfos = 145 Seq((512, 4, 6), 146 (512, 9, 6), 147 (1024, 19, 6)), 148 SCNRows = 128, 149 SCNTables = 2, 150 SCHistLens = Seq(0, 5), 151 ITTageTableInfos = 152 Seq((256, 4, 7), 153 (256, 8, 7), 154 (512, 16, 7)), 155 // ================================ 156 itlbParameters = TLBParameters( 157 name = "itlb", 158 fetchi = true, 159 useDmode = false, 160 NWays = 4, 161 ), 162 ldtlbParameters = TLBParameters( 163 name = "ldtlb", 164 NWays = 4, 165 partialStaticPMP = true, 166 outsideRecvFlush = true, 167 outReplace = false, 168 lgMaxSize = 4 169 ), 170 sttlbParameters = TLBParameters( 171 name = "sttlb", 172 NWays = 4, 173 partialStaticPMP = true, 174 outsideRecvFlush = true, 175 outReplace = false, 176 lgMaxSize = 4 177 ), 178 hytlbParameters = TLBParameters( 179 name = "hytlb", 180 NWays = 4, 181 partialStaticPMP = true, 182 outsideRecvFlush = true, 183 outReplace = false, 184 lgMaxSize = 4 185 ), 186 pftlbParameters = TLBParameters( 187 name = "pftlb", 188 NWays = 4, 189 partialStaticPMP = true, 190 outsideRecvFlush = true, 191 outReplace = false, 192 lgMaxSize = 4 193 ), 194 btlbParameters = TLBParameters( 195 name = "btlb", 196 NWays = 4, 197 ), 198 l2tlbParameters = L2TLBParameters( 199 l3Size = 4, 200 l2Size = 4, 201 l1nSets = 4, 202 l1nWays = 4, 203 l1ReservedBits = 1, 204 l0nSets = 4, 205 l0nWays = 8, 206 l0ReservedBits = 0, 207 spSize = 4, 208 ), 209 L2CacheParamsOpt = Some(L2Param( 210 name = "L2", 211 ways = 8, 212 sets = 128, 213 echoField = Seq(huancun.DirtyField()), 214 prefetch = Nil, 215 clientCaches = Seq(L1Param( 216 "dcache", 217 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 218 )), 219 )), 220 L2NBanks = 2, 221 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 222 ) 223 ) 224 case SoCParamsKey => 225 val tiles = site(XSTileKey) 226 up(SoCParamsKey).copy( 227 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 228 sets = 1024, 229 inclusive = false, 230 clientCaches = tiles.map{ core => 231 val clientDirBytes = tiles.map{ t => 232 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 233 }.sum 234 val l2params = core.L2CacheParamsOpt.get.toCacheParams 235 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 236 }, 237 simulation = !site(DebugOptionsKey).FPGAPlatform, 238 prefetch = None 239 )), 240 L3NBanks = 1 241 ) 242 }) 243) 244 245// Non-synthesizable MinimalConfig, for fast simulation only 246class MinimalSimConfig(n: Int = 1) extends Config( 247 new MinimalConfig(n).alter((site, here, up) => { 248 case XSTileKey => up(XSTileKey).map(_.copy( 249 dcacheParametersOpt = None, 250 softPTW = true 251 )) 252 case SoCParamsKey => up(SoCParamsKey).copy( 253 L3CacheParamsOpt = None 254 ) 255 }) 256) 257 258class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 259 case XSTileKey => 260 val sets = n * 1024 / ways / 64 261 up(XSTileKey).map(_.copy( 262 dcacheParametersOpt = Some(DCacheParameters( 263 nSets = sets, 264 nWays = ways, 265 tagECC = Some("secded"), 266 dataECC = Some("secded"), 267 replacer = Some("setplru"), 268 nMissEntries = 16, 269 nProbeEntries = 8, 270 nReleaseEntries = 18, 271 nMaxPrefetchEntry = 6, 272 enableTagEcc = true, 273 enableDataEcc = true, 274 cacheCtrlAddressOpt = Some(AddressSet(0x38022000, 0x7f)) 275 )) 276 )) 277}) 278 279class WithNKBL2 280( 281 n: Int, 282 ways: Int = 8, 283 inclusive: Boolean = true, 284 banks: Int = 1, 285 tp: Boolean = true 286) extends Config((site, here, up) => { 287 case XSTileKey => 288 require(inclusive, "L2 must be inclusive") 289 val upParams = up(XSTileKey) 290 val l2sets = n * 1024 / banks / ways / 64 291 upParams.map(p => p.copy( 292 L2CacheParamsOpt = Some(L2Param( 293 name = "L2", 294 ways = ways, 295 sets = l2sets, 296 clientCaches = Seq(L1Param( 297 "dcache", 298 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 299 ways = p.dcacheParametersOpt.get.nWays + 2, 300 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 301 vaddrBitsOpt = Some(p.GPAddrBitsSv48x4 - log2Up(p.dcacheParametersOpt.get.blockBytes)), 302 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 303 )), 304 reqField = Seq(utility.ReqSourceField()), 305 echoField = Seq(huancun.DirtyField()), 306 tagECC = Some("secded"), 307 dataECC = Some("secded"), 308 enableTagECC = true, 309 enableDataECC = true, 310 dataCheck = Some("oddparity"), 311 prefetch = Seq(BOPParameters()) ++ 312 (if (tp) Seq(TPParameters()) else Nil) ++ 313 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil), 314 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 315 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 316 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 317 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 318 )), 319 L2NBanks = banks 320 )) 321}) 322 323class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 324 case SoCParamsKey => 325 val sets = n * 1024 / banks / ways / 64 326 val tiles = site(XSTileKey) 327 val clientDirBytes = tiles.map{ t => 328 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 329 }.sum 330 up(SoCParamsKey).copy( 331 L3NBanks = banks, 332 L3CacheParamsOpt = Some(HCCacheParameters( 333 name = "L3", 334 level = 3, 335 ways = ways, 336 sets = sets, 337 inclusive = inclusive, 338 clientCaches = tiles.map{ core => 339 val l2params = core.L2CacheParamsOpt.get.toCacheParams 340 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 341 }, 342 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 343 ctrl = Some(CacheCtrl( 344 address = 0x39000000, 345 numCores = tiles.size 346 )), 347 reqField = Seq(utility.ReqSourceField()), 348 sramClkDivBy2 = true, 349 sramDepthDiv = 4, 350 tagECC = Some("secded"), 351 dataECC = Some("secded"), 352 simulation = !site(DebugOptionsKey).FPGAPlatform, 353 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 354 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 355 )), 356 OpenLLCParamsOpt = Some(OpenLLCParam( 357 name = "LLC", 358 ways = ways, 359 sets = sets, 360 banks = banks, 361 fullAddressBits = 48, 362 clientCaches = tiles.map { core => 363 val l2params = core.L2CacheParamsOpt.get 364 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 365 }, 366 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 367 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 368 )) 369 ) 370}) 371 372class WithL3DebugConfig extends Config( 373 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 374) 375 376class MinimalL3DebugConfig(n: Int = 1) extends Config( 377 new WithL3DebugConfig ++ new MinimalConfig(n) 378) 379 380class DefaultL3DebugConfig(n: Int = 1) extends Config( 381 new WithL3DebugConfig ++ new BaseConfig(n) 382) 383 384class WithFuzzer extends Config((site, here, up) => { 385 case DebugOptionsKey => up(DebugOptionsKey).copy( 386 EnablePerfDebug = false, 387 ) 388 case SoCParamsKey => up(SoCParamsKey).copy( 389 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 390 enablePerf = false, 391 )), 392 ) 393 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 394 p.copy( 395 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 396 enablePerf = false, 397 )), 398 ) 399 } 400}) 401 402class MinimalAliasDebugConfig(n: Int = 1) extends Config( 403 new WithNKBL3(512, inclusive = false) ++ 404 new WithNKBL2(256, inclusive = true) ++ 405 new WithNKBL1D(128) ++ 406 new MinimalConfig(n) 407) 408 409class MediumConfig(n: Int = 1) extends Config( 410 new WithNKBL3(4096, inclusive = false, banks = 4) 411 ++ new WithNKBL2(512, inclusive = true) 412 ++ new WithNKBL1D(128) 413 ++ new BaseConfig(n) 414) 415 416class FuzzConfig(dummy: Int = 0) extends Config( 417 new WithFuzzer 418 ++ new DefaultConfig(1) 419) 420 421class DefaultConfig(n: Int = 1) extends Config( 422 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 423 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 424 ++ new WithNKBL1D(64, ways = 4) 425 ++ new BaseConfig(n) 426) 427 428class WithCHI extends Config((_, _, _) => { 429 case EnableCHI => true 430}) 431 432class KunminghuV2Config(n: Int = 1) extends Config( 433 new WithCHI 434 ++ new Config((site, here, up) => { 435 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 436 }) 437 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false) 438 ++ new WithNKBL1D(64, ways = 4) 439 ++ new DefaultConfig(n) 440) 441 442class KunminghuV2MinimalConfig(n: Int = 1) extends Config( 443 new WithCHI 444 ++ new Config((site, here, up) => { 445 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 446 }) 447 ++ new WithNKBL2(128, inclusive = true, banks = 1, tp = false) 448 ++ new WithNKBL1D(32, ways = 4) 449 ++ new MinimalConfig(n) 450) 451 452class XSNoCTopConfig(n: Int = 1) extends Config( 453 (new KunminghuV2Config(n)).alter((site, here, up) => { 454 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 455 }) 456) 457 458class XSNoCTopMinimalConfig(n: Int = 1) extends Config( 459 (new KunminghuV2MinimalConfig(n)).alter((site, here, up) => { 460 case SoCParamsKey => up(SoCParamsKey).copy(UseXSNoCTop = true) 461 }) 462) 463 464class FpgaDefaultConfig(n: Int = 1) extends Config( 465 (new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6) 466 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 467 ++ new WithNKBL1D(64, ways = 4) 468 ++ new BaseConfig(n)).alter((site, here, up) => { 469 case DebugOptionsKey => up(DebugOptionsKey).copy( 470 AlwaysBasicDiff = false, 471 AlwaysBasicDB = false 472 ) 473 case SoCParamsKey => up(SoCParamsKey).copy( 474 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 475 sramClkDivBy2 = false, 476 )), 477 ) 478 }) 479) 480 481class FpgaDiffDefaultConfig(n: Int = 1) extends Config( 482 (new WithNKBL3(3 * 1024, inclusive = false, banks = 1, ways = 6) 483 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 484 ++ new WithNKBL1D(64, ways = 8) 485 ++ new BaseConfig(n)).alter((site, here, up) => { 486 case DebugOptionsKey => up(DebugOptionsKey).copy( 487 AlwaysBasicDiff = true, 488 AlwaysBasicDB = false 489 ) 490 case SoCParamsKey => up(SoCParamsKey).copy( 491 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 492 sramClkDivBy2 = false, 493 )), 494 ) 495 }) 496) 497