1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.MaxHartIdBits 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.exu.ExuParameters 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import device.{EnableJtag, XSDebugModuleParams} 35import huancun._ 36import coupledL2._ 37 38class BaseConfig(n: Int) extends Config((site, here, up) => { 39 case XLen => 64 40 case DebugOptionsKey => DebugOptions() 41 case SoCParamsKey => SoCParameters() 42 case PMParameKey => PMParameters() 43 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 44 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 45 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 46 case JtagDTMKey => JtagDTMKey 47 case MaxHartIdBits => 2 48 case EnableJtag => true.B 49}) 50 51// Synthesizable minimal XiangShan 52// * It is still an out-of-order, super-scalaer arch 53// * L1 cache included 54// * L2 cache NOT included 55// * L3 cache included 56class MinimalConfig(n: Int = 1) extends Config( 57 new BaseConfig(n).alter((site, here, up) => { 58 case XSTileKey => up(XSTileKey).map( 59 p => p.copy( 60 DecodeWidth = 2, 61 RenameWidth = 2, 62 CommitWidth = 2, 63 FetchWidth = 4, 64 IssQueSize = 8, 65 NRPhyRegs = 64, 66 VirtualLoadQueueSize = 16, 67 LoadQueueRARSize = 16, 68 LoadQueueRAWSize = 12, 69 LoadQueueReplaySize = 12, 70 LoadUncacheBufferSize = 8, 71 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 72 RollbackGroupSize = 8, 73 StoreQueueSize = 12, 74 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 75 StoreQueueForwardWithMask = true, 76 RobSize = 32, 77 FtqSize = 8, 78 IBufSize = 16, 79 IBufNBank = 2, 80 StoreBufferSize = 4, 81 StoreBufferThreshold = 3, 82 LoadPipelineWidth = 2, 83 StorePipelineWidth = 2, 84 dpParams = DispatchParameters( 85 IntDqSize = 12, 86 FpDqSize = 12, 87 LsDqSize = 12, 88 IntDqDeqWidth = 4, 89 FpDqDeqWidth = 4, 90 LsDqDeqWidth = 4 91 ), 92 exuParameters = ExuParameters( 93 JmpCnt = 1, 94 AluCnt = 2, 95 MulCnt = 0, 96 MduCnt = 1, 97 FmacCnt = 1, 98 FmiscCnt = 1, 99 FmiscDivSqrtCnt = 0, 100 LduCnt = 2, 101 StuCnt = 2 102 ), 103 icacheParameters = ICacheParameters( 104 nSets = 64, // 16KB ICache 105 tagECC = Some("parity"), 106 dataECC = Some("parity"), 107 replacer = Some("setplru"), 108 nMissEntries = 2, 109 nReleaseEntries = 1, 110 nProbeEntries = 2, 111 // fdip 112 enableICachePrefetch = true, 113 prefetchToL1 = false, 114 ), 115 dcacheParametersOpt = Some(DCacheParameters( 116 nSets = 64, // 32KB DCache 117 nWays = 8, 118 tagECC = Some("secded"), 119 dataECC = Some("secded"), 120 replacer = Some("setplru"), 121 nMissEntries = 4, 122 nProbeEntries = 4, 123 nReleaseEntries = 8, 124 nMaxPrefetchEntry = 2, 125 )), 126 EnableBPD = false, // disable TAGE 127 EnableLoop = false, 128 itlbParameters = TLBParameters( 129 name = "itlb", 130 fetchi = true, 131 useDmode = false, 132 NWays = 4, 133 ), 134 ldtlbParameters = TLBParameters( 135 name = "ldtlb", 136 NWays = 4, 137 partialStaticPMP = true, 138 outsideRecvFlush = true, 139 outReplace = false 140 ), 141 sttlbParameters = TLBParameters( 142 name = "sttlb", 143 NWays = 4, 144 partialStaticPMP = true, 145 outsideRecvFlush = true, 146 outReplace = false 147 ), 148 pftlbParameters = TLBParameters( 149 name = "pftlb", 150 NWays = 4, 151 partialStaticPMP = true, 152 outsideRecvFlush = true, 153 outReplace = false 154 ), 155 btlbParameters = TLBParameters( 156 name = "btlb", 157 NWays = 4, 158 ), 159 l2tlbParameters = L2TLBParameters( 160 l1Size = 4, 161 l2nSets = 4, 162 l2nWays = 4, 163 l3nSets = 4, 164 l3nWays = 8, 165 spSize = 2, 166 ), 167 L2CacheParamsOpt = Some(L2Param( 168 name = "L2", 169 ways = 8, 170 sets = 128, 171 echoField = Seq(huancun.DirtyField()), 172 prefetch = None, 173 clientCaches = Seq(L1Param( 174 "dcache", 175 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 176 )), 177 ) 178 ), 179 L2NBanks = 2, 180 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 181 ) 182 ) 183 case SoCParamsKey => 184 val tiles = site(XSTileKey) 185 up(SoCParamsKey).copy( 186 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 187 sets = 1024, 188 inclusive = false, 189 clientCaches = tiles.map{ core => 190 val clientDirBytes = tiles.map{ t => 191 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 192 }.sum 193 val l2params = core.L2CacheParamsOpt.get.toCacheParams 194 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 195 }, 196 simulation = !site(DebugOptionsKey).FPGAPlatform, 197 prefetch = None 198 )), 199 L3NBanks = 1 200 ) 201 }) 202) 203 204// Non-synthesizable MinimalConfig, for fast simulation only 205class MinimalSimConfig(n: Int = 1) extends Config( 206 new MinimalConfig(n).alter((site, here, up) => { 207 case XSTileKey => up(XSTileKey).map(_.copy( 208 dcacheParametersOpt = None, 209 softPTW = true 210 )) 211 case SoCParamsKey => up(SoCParamsKey).copy( 212 L3CacheParamsOpt = None 213 ) 214 }) 215) 216 217class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 218 case XSTileKey => 219 val sets = n * 1024 / ways / 64 220 up(XSTileKey).map(_.copy( 221 dcacheParametersOpt = Some(DCacheParameters( 222 nSets = sets, 223 nWays = ways, 224 tagECC = Some("secded"), 225 dataECC = Some("secded"), 226 replacer = Some("setplru"), 227 nMissEntries = 16, 228 nProbeEntries = 8, 229 nReleaseEntries = 18, 230 nMaxPrefetchEntry = 6, 231 )) 232 )) 233}) 234 235class WithNKBL2 236( 237 n: Int, 238 ways: Int = 8, 239 inclusive: Boolean = true, 240 banks: Int = 1 241) extends Config((site, here, up) => { 242 case XSTileKey => 243 require(inclusive, "L2 must be inclusive") 244 val upParams = up(XSTileKey) 245 val l2sets = n * 1024 / banks / ways / 64 246 upParams.map(p => p.copy( 247 L2CacheParamsOpt = Some(L2Param( 248 name = "L2", 249 ways = ways, 250 sets = l2sets, 251 clientCaches = Seq(L1Param( 252 "dcache", 253 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 254 ways = p.dcacheParametersOpt.get.nWays + 2, 255 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 256 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)), 257 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 258 )), 259 reqField = Seq(utility.ReqSourceField()), 260 echoField = Seq(huancun.DirtyField()), 261 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()), 262 enablePerf = !site(DebugOptionsKey).FPGAPlatform, 263 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 264 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 265 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 266 )), 267 L2NBanks = banks 268 )) 269}) 270 271class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 272 case SoCParamsKey => 273 val sets = n * 1024 / banks / ways / 64 274 val tiles = site(XSTileKey) 275 val clientDirBytes = tiles.map{ t => 276 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 277 }.sum 278 up(SoCParamsKey).copy( 279 L3NBanks = banks, 280 L3CacheParamsOpt = Some(HCCacheParameters( 281 name = "L3", 282 level = 3, 283 ways = ways, 284 sets = sets, 285 inclusive = inclusive, 286 clientCaches = tiles.map{ core => 287 val l2params = core.L2CacheParamsOpt.get.toCacheParams 288 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 289 }, 290 enablePerf = true, 291 ctrl = Some(CacheCtrl( 292 address = 0x39000000, 293 numCores = tiles.size 294 )), 295 reqField = Seq(utility.ReqSourceField()), 296 sramClkDivBy2 = true, 297 sramDepthDiv = 4, 298 tagECC = Some("secded"), 299 dataECC = Some("secded"), 300 simulation = !site(DebugOptionsKey).FPGAPlatform, 301 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 302 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 303 )) 304 ) 305}) 306 307class WithL3DebugConfig extends Config( 308 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 309) 310 311class MinimalL3DebugConfig(n: Int = 1) extends Config( 312 new WithL3DebugConfig ++ new MinimalConfig(n) 313) 314 315class DefaultL3DebugConfig(n: Int = 1) extends Config( 316 new WithL3DebugConfig ++ new BaseConfig(n) 317) 318 319class WithFuzzer extends Config((site, here, up) => { 320 case DebugOptionsKey => up(DebugOptionsKey).copy( 321 EnablePerfDebug = false, 322 ) 323 case SoCParamsKey => up(SoCParamsKey).copy( 324 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 325 enablePerf = false, 326 )), 327 ) 328 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 329 p.copy( 330 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 331 enablePerf = false, 332 )), 333 ) 334 } 335}) 336 337class MinimalAliasDebugConfig(n: Int = 1) extends Config( 338 new WithNKBL3(512, inclusive = false) ++ 339 new WithNKBL2(256, inclusive = true) ++ 340 new WithNKBL1D(128) ++ 341 new MinimalConfig(n) 342) 343 344class MediumConfig(n: Int = 1) extends Config( 345 new WithNKBL3(4096, inclusive = false, banks = 4) 346 ++ new WithNKBL2(512, inclusive = true) 347 ++ new WithNKBL1D(128) 348 ++ new BaseConfig(n) 349) 350 351class FuzzConfig(dummy: Int = 0) extends Config( 352 new WithFuzzer 353 ++ new DefaultConfig(1) 354) 355 356class DefaultConfig(n: Int = 1) extends Config( 357 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 358 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 359 ++ new WithNKBL1D(64, ways = 4) 360 ++ new BaseConfig(n) 361) 362