1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import xiangshan.frontend.icache.ICacheParameters 27import freechips.rocketchip.devices.debug._ 28import freechips.rocketchip.tile.MaxHartIdBits 29import xiangshan.backend.dispatch.DispatchParameters 30import xiangshan.backend.exu.ExuParameters 31import xiangshan.cache.DCacheParameters 32import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 33import device.{EnableJtag, XSDebugModuleParams} 34import huancun._ 35 36class BaseConfig(n: Int) extends Config((site, here, up) => { 37 case XLen => 64 38 case DebugOptionsKey => DebugOptions() 39 case SoCParamsKey => SoCParameters() 40 case PMParameKey => PMParameters() 41 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 42 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 43 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 44 case JtagDTMKey => JtagDTMKey 45 case MaxHartIdBits => 2 46 case EnableJtag => true.B 47}) 48 49// Synthesizable minimal XiangShan 50// * It is still an out-of-order, super-scalaer arch 51// * L1 cache included 52// * L2 cache NOT included 53// * L3 cache included 54class MinimalConfig(n: Int = 1) extends Config( 55 new BaseConfig(n).alter((site, here, up) => { 56 case XSTileKey => up(XSTileKey).map( 57 _.copy( 58 DecodeWidth = 2, 59 RenameWidth = 2, 60 FetchWidth = 4, 61 IssQueSize = 8, 62 NRPhyRegs = 64, 63 LoadQueueSize = 16, 64 StoreQueueSize = 12, 65 RobSize = 32, 66 FtqSize = 8, 67 IBufSize = 16, 68 StoreBufferSize = 4, 69 StoreBufferThreshold = 3, 70 dpParams = DispatchParameters( 71 IntDqSize = 12, 72 FpDqSize = 12, 73 LsDqSize = 12, 74 IntDqDeqWidth = 4, 75 FpDqDeqWidth = 4, 76 LsDqDeqWidth = 4 77 ), 78 exuParameters = ExuParameters( 79 JmpCnt = 1, 80 AluCnt = 2, 81 MulCnt = 0, 82 MduCnt = 1, 83 FmacCnt = 1, 84 FmiscCnt = 1, 85 FmiscDivSqrtCnt = 0, 86 LduCnt = 2, 87 StuCnt = 2 88 ), 89 icacheParameters = ICacheParameters( 90 nSets = 64, // 16KB ICache 91 tagECC = Some("parity"), 92 dataECC = Some("parity"), 93 replacer = Some("setplru"), 94 nMissEntries = 2, 95 nReleaseEntries = 1, 96 nProbeEntries = 2, 97 nPrefetchEntries = 2, 98 hasPrefetch = false 99 ), 100 dcacheParametersOpt = Some(DCacheParameters( 101 nSets = 64, // 32KB DCache 102 nWays = 8, 103 tagECC = Some("secded"), 104 dataECC = Some("secded"), 105 replacer = Some("setplru"), 106 nMissEntries = 4, 107 nProbeEntries = 4, 108 nReleaseEntries = 8, 109 )), 110 EnableBPD = false, // disable TAGE 111 EnableLoop = false, 112 itlbParameters = TLBParameters( 113 name = "itlb", 114 fetchi = true, 115 useDmode = false, 116 sameCycle = false, 117 missSameCycle = true, 118 normalReplacer = Some("plru"), 119 superReplacer = Some("plru"), 120 normalNWays = 4, 121 normalNSets = 1, 122 superNWays = 2, 123 shouldBlock = true 124 ), 125 ldtlbParameters = TLBParameters( 126 name = "ldtlb", 127 normalNSets = 4, // when da or sa 128 normalNWays = 1, // when fa or sa 129 normalAssociative = "sa", 130 normalReplacer = Some("setplru"), 131 superNWays = 4, 132 normalAsVictim = true, 133 partialStaticPMP = true, 134 outReplace = true 135 ), 136 sttlbParameters = TLBParameters( 137 name = "sttlb", 138 normalNSets = 4, // when da or sa 139 normalNWays = 1, // when fa or sa 140 normalAssociative = "sa", 141 normalReplacer = Some("setplru"), 142 normalAsVictim = true, 143 superNWays = 4, 144 partialStaticPMP = true, 145 outReplace = true 146 ), 147 btlbParameters = TLBParameters( 148 name = "btlb", 149 normalNSets = 1, 150 normalNWays = 8, 151 superNWays = 2 152 ), 153 l2tlbParameters = L2TLBParameters( 154 l1Size = 4, 155 l2nSets = 4, 156 l2nWays = 4, 157 l3nSets = 4, 158 l3nWays = 8, 159 spSize = 2, 160 ), 161 L2CacheParamsOpt = None // remove L2 Cache 162 ) 163 ) 164 case SoCParamsKey => up(SoCParamsKey).copy( 165 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 166 sets = 1024 167 )), 168 L3NBanks = 1 169 ) 170 }) 171) 172 173// Non-synthesizable MinimalConfig, for fast simulation only 174class MinimalSimConfig(n: Int = 1) extends Config( 175 new MinimalConfig(n).alter((site, here, up) => { 176 case XSTileKey => up(XSTileKey).map(_.copy( 177 dcacheParametersOpt = None, 178 softPTW = true 179 )) 180 case SoCParamsKey => up(SoCParamsKey).copy( 181 L3CacheParamsOpt = None 182 ) 183 }) 184) 185 186class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 187 case XSTileKey => 188 val sets = n * 1024 / ways / 64 189 up(XSTileKey).map(_.copy( 190 dcacheParametersOpt = Some(DCacheParameters( 191 nSets = sets, 192 nWays = ways, 193 tagECC = Some("secded"), 194 dataECC = Some("secded"), 195 replacer = Some("setplru"), 196 nMissEntries = 16, 197 nProbeEntries = 8, 198 nReleaseEntries = 18 199 )) 200 )) 201}) 202 203class WithNKBL2 204( 205 n: Int, 206 ways: Int = 8, 207 inclusive: Boolean = true, 208 banks: Int = 1, 209 alwaysReleaseData: Boolean = false 210) extends Config((site, here, up) => { 211 case XSTileKey => 212 val upParams = up(XSTileKey) 213 val l2sets = n * 1024 / banks / ways / 64 214 upParams.map(p => p.copy( 215 L2CacheParamsOpt = Some(HCCacheParameters( 216 name = "L2", 217 level = 2, 218 ways = ways, 219 sets = l2sets, 220 inclusive = inclusive, 221 alwaysReleaseData = alwaysReleaseData, 222 clientCaches = Seq(CacheParameters( 223 "dcache", 224 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 225 ways = p.dcacheParametersOpt.get.nWays + 2, 226 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 227 )), 228 reqField = Seq(PreferCacheField()), 229 echoField = Seq(DirtyField()), 230 prefetch = Some(huancun.prefetch.BOPParameters()), 231 enablePerf = true, 232 sramDepthDiv = 2, 233 tagECC = Some("secded"), 234 dataECC = Some("secded") 235 )), 236 L2NBanks = banks 237 )) 238}) 239 240class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 241 case SoCParamsKey => 242 val sets = n * 1024 / banks / ways / 64 243 val tiles = site(XSTileKey) 244 val clientDirBytes = tiles.map{ t => 245 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 246 }.sum 247 up(SoCParamsKey).copy( 248 L3NBanks = banks, 249 L3CacheParamsOpt = Some(HCCacheParameters( 250 name = "L3", 251 level = 3, 252 ways = ways, 253 sets = sets, 254 inclusive = inclusive, 255 clientCaches = tiles.map{ core => 256 val l2params = core.L2CacheParamsOpt.get.toCacheParams 257 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 258 }, 259 enablePerf = true, 260 ctrl = Some(CacheCtrl( 261 address = 0x39000000, 262 numCores = tiles.size 263 )), 264 sramClkDivBy2 = true, 265 sramDepthDiv = 4, 266 tagECC = Some("secded"), 267 dataECC = Some("secded") 268 )) 269 ) 270}) 271 272class WithL3DebugConfig extends Config( 273 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 274) 275 276class MinimalL3DebugConfig(n: Int = 1) extends Config( 277 new WithL3DebugConfig ++ new MinimalConfig(n) 278) 279 280class DefaultL3DebugConfig(n: Int = 1) extends Config( 281 new WithL3DebugConfig ++ new BaseConfig(n) 282) 283 284class MinimalAliasDebugConfig(n: Int = 1) extends Config( 285 new WithNKBL3(512, inclusive = false) ++ 286 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 287 new WithNKBL1D(128) ++ 288 new MinimalConfig(n) 289) 290 291class MediumConfig(n: Int = 1) extends Config( 292 new WithNKBL3(4096, inclusive = false, banks = 4) 293 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 294 ++ new WithNKBL1D(128) 295 ++ new BaseConfig(n) 296) 297 298class DefaultConfig(n: Int = 1) extends Config( 299 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 300 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 301 ++ new WithNKBL1D(128) 302 ++ new BaseConfig(n) 303) 304