xref: /XiangShan/src/main/scala/top/Configs.scala (revision 39c59369af6e7d78fa72e13aae3735f1a6e98f5c)
1c6d43980SLemover/***************************************************************************************
2c6d43980SLemover* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3f320e0f0SYinan Xu* Copyright (c) 2020-2021 Peng Cheng Laboratory
4c6d43980SLemover*
5c6d43980SLemover* XiangShan is licensed under Mulan PSL v2.
6c6d43980SLemover* You can use this software according to the terms and conditions of the Mulan PSL v2.
7c6d43980SLemover* You may obtain a copy of Mulan PSL v2 at:
8c6d43980SLemover*          http://license.coscl.org.cn/MulanPSL2
9c6d43980SLemover*
10c6d43980SLemover* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11c6d43980SLemover* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12c6d43980SLemover* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13c6d43980SLemover*
14c6d43980SLemover* See the Mulan PSL v2 for more details.
15c6d43980SLemover***************************************************************************************/
16c6d43980SLemover
1745c767e3SLinJiaweipackage top
1845c767e3SLinJiawei
193b739f49SXuan Huimport chipsalliance.rocketchip.config._
2045c767e3SLinJiaweiimport chisel3._
2145c767e3SLinJiaweiimport chisel3.util._
223b739f49SXuan Huimport device.{EnableJtag, XSDebugModuleParams}
23d4aca96cSlqreimport freechips.rocketchip.devices.debug._
243b739f49SXuan Huimport freechips.rocketchip.tile.{MaxHartIdBits, XLen}
253b739f49SXuan Huimport system._
263b739f49SXuan Huimport utility._
273b739f49SXuan Huimport utils._
283b739f49SXuan Huimport huancun._
293b739f49SXuan Huimport xiangshan._
3045c767e3SLinJiaweiimport xiangshan.backend.dispatch.DispatchParameters
31730cfbc0SXuan Huimport xiangshan.backend.regfile.{IntPregParams, VfPregParams}
321f0e2dc7SJiawei Linimport xiangshan.cache.DCacheParameters
33a0301c0dSLemoverimport xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
34a1ea7f76SJiawei Linimport device.{EnableJtag, XSDebugModuleParams}
351f0e2dc7SJiawei Linimport huancun._
3615ee59e4Swakafaimport coupledL2._
373b739f49SXuan Huimport xiangshan.frontend.icache.ICacheParameters
3845c767e3SLinJiawei
391f0e2dc7SJiawei Linclass BaseConfig(n: Int) extends Config((site, here, up) => {
4045c767e3SLinJiawei  case XLen => 64
4145c767e3SLinJiawei  case DebugOptionsKey => DebugOptions()
4234ab1ae9SJiawei Lin  case SoCParamsKey => SoCParameters()
4398c71602SJiawei Lin  case PMParameKey => PMParameters()
4434ab1ae9SJiawei Lin  case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) }
45d4aca96cSlqre  case ExportDebug => DebugAttachParams(protocols = Set(JTAG))
46d4aca96cSlqre  case DebugModuleKey => Some(XSDebugModuleParams(site(XLen)))
47d4aca96cSlqre  case JtagDTMKey => JtagDTMKey
48d4aca96cSlqre  case MaxHartIdBits => 2
49f1c56d6cSLi Qianruo  case EnableJtag => true.B
5045c767e3SLinJiawei})
5145c767e3SLinJiawei
5205f23f57SWilliam Wang// Synthesizable minimal XiangShan
5305f23f57SWilliam Wang// * It is still an out-of-order, super-scalaer arch
5405f23f57SWilliam Wang// * L1 cache included
5505f23f57SWilliam Wang// * L2 cache NOT included
5605f23f57SWilliam Wang// * L3 cache included
5745c767e3SLinJiaweiclass MinimalConfig(n: Int = 1) extends Config(
581f0e2dc7SJiawei Lin  new BaseConfig(n).alter((site, here, up) => {
5934ab1ae9SJiawei Lin    case XSTileKey => up(XSTileKey).map(
6034ab1ae9SJiawei Lin      _.copy(
6105f23f57SWilliam Wang        DecodeWidth = 2,
6205f23f57SWilliam Wang        RenameWidth = 2,
63ccfddc82SHaojin Tang        CommitWidth = 2,
6405f23f57SWilliam Wang        FetchWidth = 4,
65e4f69d78Ssfencevma        VirtualLoadQueueSize = 16,
66e4f69d78Ssfencevma        LoadQueueRARSize = 16,
67e4f69d78Ssfencevma        LoadQueueRAWSize = 12,
68e4f69d78Ssfencevma        LoadQueueReplaySize = 8,
69e4f69d78Ssfencevma        LoadUncacheBufferSize = 8,
70e4f69d78Ssfencevma        LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks.
71e4f69d78Ssfencevma        RollbackGroupSize = 8,
723a6496e9SYinan Xu        StoreQueueSize = 12,
73e4f69d78Ssfencevma        StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks
74e4f69d78Ssfencevma        StoreQueueForwardWithMask = true,
759aca92b9SYinan Xu        RobSize = 32,
763a6496e9SYinan Xu        FtqSize = 8,
7745c767e3SLinJiawei        IBufSize = 16,
7805f23f57SWilliam Wang        StoreBufferSize = 4,
7905f23f57SWilliam Wang        StoreBufferThreshold = 3,
8045c767e3SLinJiawei        dpParams = DispatchParameters(
813a6496e9SYinan Xu          IntDqSize = 12,
823a6496e9SYinan Xu          FpDqSize = 12,
833a6496e9SYinan Xu          LsDqSize = 12,
8445c767e3SLinJiawei          IntDqDeqWidth = 4,
8545c767e3SLinJiawei          FpDqDeqWidth = 4,
8645c767e3SLinJiawei          LsDqDeqWidth = 4
8745c767e3SLinJiawei        ),
883b739f49SXuan Hu        intPreg = IntPregParams(
89*39c59369SXuan Hu          numEntries = 64,
90*39c59369SXuan Hu          numRead = Some(14),
91*39c59369SXuan Hu          numWrite = Some(8),
923b739f49SXuan Hu        ),
933b739f49SXuan Hu        vfPreg = VfPregParams(
94*39c59369SXuan Hu          numEntries = 96,
95*39c59369SXuan Hu          numRead = Some(14),
96*39c59369SXuan Hu          numWrite = Some(8),
973a6496e9SYinan Xu        ),
9805f23f57SWilliam Wang        icacheParameters = ICacheParameters(
993a6496e9SYinan Xu          nSets = 64, // 16KB ICache
10005f23f57SWilliam Wang          tagECC = Some("parity"),
10105f23f57SWilliam Wang          dataECC = Some("parity"),
10205f23f57SWilliam Wang          replacer = Some("setplru"),
1031d8f4dcbSJay          nMissEntries = 2,
10400240ba6SJay          nReleaseEntries = 1,
1057052722fSJay          nProbeEntries = 2,
106a108d429SJay          nPrefetchEntries = 2,
107b1ded4e8Sguohongyu          nPrefBufferEntries = 32,
108b1ded4e8Sguohongyu          hasPrefetch = true
10905f23f57SWilliam Wang        ),
1104f94c0c6SJiawei Lin        dcacheParametersOpt = Some(DCacheParameters(
1114f94c0c6SJiawei Lin          nSets = 64, // 32KB DCache
1123a6496e9SYinan Xu          nWays = 8,
11305f23f57SWilliam Wang          tagECC = Some("secded"),
11405f23f57SWilliam Wang          dataECC = Some("secded"),
11505f23f57SWilliam Wang          replacer = Some("setplru"),
11605f23f57SWilliam Wang          nMissEntries = 4,
11705f23f57SWilliam Wang          nProbeEntries = 4,
118ad3ba452Szhanglinjuan          nReleaseEntries = 8,
1194f94c0c6SJiawei Lin        )),
12045c767e3SLinJiawei        EnableBPD = false, // disable TAGE
12145c767e3SLinJiawei        EnableLoop = false,
122a0301c0dSLemover        itlbParameters = TLBParameters(
123a0301c0dSLemover          name = "itlb",
124a0301c0dSLemover          fetchi = true,
125a0301c0dSLemover          useDmode = false,
126a0301c0dSLemover          normalReplacer = Some("plru"),
127a0301c0dSLemover          superReplacer = Some("plru"),
128a0301c0dSLemover          normalNWays = 4,
129a0301c0dSLemover          normalNSets = 1,
130f1fe8698SLemover          superNWays = 2
131a0301c0dSLemover        ),
132a0301c0dSLemover        ldtlbParameters = TLBParameters(
133a0301c0dSLemover          name = "ldtlb",
13403efd994Shappy-lx          normalNSets = 16, // when da or sa
135a0301c0dSLemover          normalNWays = 1, // when fa or sa
136a0301c0dSLemover          normalAssociative = "sa",
137a0301c0dSLemover          normalReplacer = Some("setplru"),
138a0301c0dSLemover          superNWays = 4,
139a0301c0dSLemover          normalAsVictim = true,
1405b7ef044SLemover          partialStaticPMP = true,
141f1fe8698SLemover          outsideRecvFlush = true,
14253b8f1a7SLemover          outReplace = false
143a0301c0dSLemover        ),
144a0301c0dSLemover        sttlbParameters = TLBParameters(
145a0301c0dSLemover          name = "sttlb",
14603efd994Shappy-lx          normalNSets = 16, // when da or sa
147a0301c0dSLemover          normalNWays = 1, // when fa or sa
148a0301c0dSLemover          normalAssociative = "sa",
149a0301c0dSLemover          normalReplacer = Some("setplru"),
150a0301c0dSLemover          normalAsVictim = true,
151a0301c0dSLemover          superNWays = 4,
1525b7ef044SLemover          partialStaticPMP = true,
153f1fe8698SLemover          outsideRecvFlush = true,
15453b8f1a7SLemover          outReplace = false
155a0301c0dSLemover        ),
15663632028SHaoyuan Feng        pftlbParameters = TLBParameters(
15763632028SHaoyuan Feng          name = "pftlb",
15863632028SHaoyuan Feng          normalNSets = 16, // when da or sa
15963632028SHaoyuan Feng          normalNWays = 1, // when fa or sa
16063632028SHaoyuan Feng          normalAssociative = "sa",
16163632028SHaoyuan Feng          normalReplacer = Some("setplru"),
16263632028SHaoyuan Feng          normalAsVictim = true,
16363632028SHaoyuan Feng          superNWays = 4,
16463632028SHaoyuan Feng          partialStaticPMP = true,
16563632028SHaoyuan Feng          outsideRecvFlush = true,
16663632028SHaoyuan Feng          outReplace = false
16763632028SHaoyuan Feng        ),
168a0301c0dSLemover        btlbParameters = TLBParameters(
169a0301c0dSLemover          name = "btlb",
170a0301c0dSLemover          normalNSets = 1,
171a0301c0dSLemover          normalNWays = 8,
172a0301c0dSLemover          superNWays = 2
173a0301c0dSLemover        ),
1745854c1edSLemover        l2tlbParameters = L2TLBParameters(
1755854c1edSLemover          l1Size = 4,
1765854c1edSLemover          l2nSets = 4,
1775854c1edSLemover          l2nWays = 4,
1785854c1edSLemover          l3nSets = 4,
1795854c1edSLemover          l3nWays = 8,
1805854c1edSLemover          spSize = 2,
1815854c1edSLemover        ),
18215ee59e4Swakafa        L2CacheParamsOpt = Some(L2Param(
18315ee59e4Swakafa          name = "L2",
18415ee59e4Swakafa          ways = 8,
18515ee59e4Swakafa          sets = 128,
18615ee59e4Swakafa          echoField = Seq(huancun.DirtyField()),
18715ee59e4Swakafa          prefetch = None
18815ee59e4Swakafa        )),
18915ee59e4Swakafa        L2NBanks = 2,
1904722e882SWilliam Wang        prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher
19134ab1ae9SJiawei Lin      )
19234ab1ae9SJiawei Lin    )
19392a50c73Swakafa    case SoCParamsKey =>
19492a50c73Swakafa      val tiles = site(XSTileKey)
19592a50c73Swakafa      up(SoCParamsKey).copy(
1964f94c0c6SJiawei Lin        L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy(
1975f79ba13Swakafa          sets = 1024,
19892a50c73Swakafa          inclusive = false,
19915ee59e4Swakafa          clientCaches = tiles.map{ core =>
20015ee59e4Swakafa            val clientDirBytes = tiles.map{ t =>
20115ee59e4Swakafa              t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0)
20215ee59e4Swakafa            }.sum
20315ee59e4Swakafa            val l2params = core.L2CacheParamsOpt.get.toCacheParams
20415ee59e4Swakafa            l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64)
20592a50c73Swakafa          },
20692a50c73Swakafa          simulation = !site(DebugOptionsKey).FPGAPlatform
2074f94c0c6SJiawei Lin        )),
208a1ea7f76SJiawei Lin        L3NBanks = 1
20905f23f57SWilliam Wang      )
21005f23f57SWilliam Wang  })
21105f23f57SWilliam Wang)
21205f23f57SWilliam Wang
21305f23f57SWilliam Wang// Non-synthesizable MinimalConfig, for fast simulation only
21405f23f57SWilliam Wangclass MinimalSimConfig(n: Int = 1) extends Config(
21505f23f57SWilliam Wang  new MinimalConfig(n).alter((site, here, up) => {
21634ab1ae9SJiawei Lin    case XSTileKey => up(XSTileKey).map(_.copy(
2174f94c0c6SJiawei Lin      dcacheParametersOpt = None,
2184f94c0c6SJiawei Lin      softPTW = true
21934ab1ae9SJiawei Lin    ))
22034ab1ae9SJiawei Lin    case SoCParamsKey => up(SoCParamsKey).copy(
2214f94c0c6SJiawei Lin      L3CacheParamsOpt = None
22245c767e3SLinJiawei    )
22345c767e3SLinJiawei  })
22445c767e3SLinJiawei)
22588825c5cSYinan Xu
2261f0e2dc7SJiawei Linclass WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => {
22734ab1ae9SJiawei Lin  case XSTileKey =>
2281f0e2dc7SJiawei Lin    val sets = n * 1024 / ways / 64
22934ab1ae9SJiawei Lin    up(XSTileKey).map(_.copy(
2304f94c0c6SJiawei Lin      dcacheParametersOpt = Some(DCacheParameters(
2311f0e2dc7SJiawei Lin        nSets = sets,
2324f94c0c6SJiawei Lin        nWays = ways,
2334f94c0c6SJiawei Lin        tagECC = Some("secded"),
2344f94c0c6SJiawei Lin        dataECC = Some("secded"),
2354f94c0c6SJiawei Lin        replacer = Some("setplru"),
2364f94c0c6SJiawei Lin        nMissEntries = 16,
237300ded30SWilliam Wang        nProbeEntries = 8,
238300ded30SWilliam Wang        nReleaseEntries = 18
2394f94c0c6SJiawei Lin      ))
24034ab1ae9SJiawei Lin    ))
2414f94c0c6SJiawei Lin})
2421f0e2dc7SJiawei Lin
243d5be5d19SJiawei Linclass WithNKBL2
244d5be5d19SJiawei Lin(
245d5be5d19SJiawei Lin  n: Int,
246d5be5d19SJiawei Lin  ways: Int = 8,
247d5be5d19SJiawei Lin  inclusive: Boolean = true,
248d5be5d19SJiawei Lin  banks: Int = 1,
249d5be5d19SJiawei Lin  alwaysReleaseData: Boolean = false
250d5be5d19SJiawei Lin) extends Config((site, here, up) => {
25134ab1ae9SJiawei Lin  case XSTileKey =>
25234ab1ae9SJiawei Lin    val upParams = up(XSTileKey)
253d5be5d19SJiawei Lin    val l2sets = n * 1024 / banks / ways / 64
25434ab1ae9SJiawei Lin    upParams.map(p => p.copy(
25515ee59e4Swakafa      L2CacheParamsOpt = Some(L2Param(
256a1ea7f76SJiawei Lin        name = "L2",
257a1ea7f76SJiawei Lin        ways = ways,
258a1ea7f76SJiawei Lin        sets = l2sets,
25915ee59e4Swakafa        clientCaches = Seq(L1Param(
2601f0e2dc7SJiawei Lin          "dcache",
261459ad1b2SJiawei Lin          sets = 2 * p.dcacheParametersOpt.get.nSets / banks,
2624f94c0c6SJiawei Lin          ways = p.dcacheParametersOpt.get.nWays + 2,
2634f94c0c6SJiawei Lin          aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt
2641f0e2dc7SJiawei Lin        )),
26515ee59e4Swakafa        echoField = Seq(huancun.DirtyField()),
26615ee59e4Swakafa        prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams())
26734ab1ae9SJiawei Lin      )),
26834ab1ae9SJiawei Lin      L2NBanks = banks
269d5be5d19SJiawei Lin    ))
270a1ea7f76SJiawei Lin})
271a1ea7f76SJiawei Lin
272a1ea7f76SJiawei Linclass WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => {
273a1ea7f76SJiawei Lin  case SoCParamsKey =>
274a1ea7f76SJiawei Lin    val sets = n * 1024 / banks / ways / 64
27534ab1ae9SJiawei Lin    val tiles = site(XSTileKey)
276459ad1b2SJiawei Lin    val clientDirBytes = tiles.map{ t =>
277459ad1b2SJiawei Lin      t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0)
278459ad1b2SJiawei Lin    }.sum
27934ab1ae9SJiawei Lin    up(SoCParamsKey).copy(
280a1ea7f76SJiawei Lin      L3NBanks = banks,
2814f94c0c6SJiawei Lin      L3CacheParamsOpt = Some(HCCacheParameters(
282a1ea7f76SJiawei Lin        name = "L3",
283a1ea7f76SJiawei Lin        level = 3,
284a1ea7f76SJiawei Lin        ways = ways,
285a1ea7f76SJiawei Lin        sets = sets,
286a1ea7f76SJiawei Lin        inclusive = inclusive,
28734ab1ae9SJiawei Lin        clientCaches = tiles.map{ core =>
2884f94c0c6SJiawei Lin          val l2params = core.L2CacheParamsOpt.get.toCacheParams
289459ad1b2SJiawei Lin          l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64)
2901f0e2dc7SJiawei Lin        },
29134ab1ae9SJiawei Lin        enablePerf = true,
29234ab1ae9SJiawei Lin        ctrl = Some(CacheCtrl(
29334ab1ae9SJiawei Lin          address = 0x39000000,
29434ab1ae9SJiawei Lin          numCores = tiles.size
29559239bc9SJiawei Lin        )),
296459ad1b2SJiawei Lin        sramClkDivBy2 = true,
2970fbed464SJiawei Lin        sramDepthDiv = 4,
298459ad1b2SJiawei Lin        tagECC = Some("secded"),
29925cb35b6SJiawei Lin        dataECC = Some("secded"),
30025cb35b6SJiawei Lin        simulation = !site(DebugOptionsKey).FPGAPlatform
3014f94c0c6SJiawei Lin      ))
302a1ea7f76SJiawei Lin    )
303a1ea7f76SJiawei Lin})
304a1ea7f76SJiawei Lin
305a1ea7f76SJiawei Linclass WithL3DebugConfig extends Config(
306a1ea7f76SJiawei Lin  new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64)
307a1ea7f76SJiawei Lin)
308a1ea7f76SJiawei Lin
309a1ea7f76SJiawei Linclass MinimalL3DebugConfig(n: Int = 1) extends Config(
310a1ea7f76SJiawei Lin  new WithL3DebugConfig ++ new MinimalConfig(n)
311a1ea7f76SJiawei Lin)
312a1ea7f76SJiawei Lin
313a1ea7f76SJiawei Linclass DefaultL3DebugConfig(n: Int = 1) extends Config(
3141f0e2dc7SJiawei Lin  new WithL3DebugConfig ++ new BaseConfig(n)
315a1ea7f76SJiawei Lin)
316a1ea7f76SJiawei Lin
3171f0e2dc7SJiawei Linclass MinimalAliasDebugConfig(n: Int = 1) extends Config(
3181f0e2dc7SJiawei Lin  new WithNKBL3(512, inclusive = false) ++
3191f0e2dc7SJiawei Lin    new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++
3201f0e2dc7SJiawei Lin    new WithNKBL1D(128) ++
3211f0e2dc7SJiawei Lin    new MinimalConfig(n)
3221f0e2dc7SJiawei Lin)
3231f0e2dc7SJiawei Lin
324496c0adfSJiawei Linclass MediumConfig(n: Int = 1) extends Config(
3251f0e2dc7SJiawei Lin  new WithNKBL3(4096, inclusive = false, banks = 4)
3261f0e2dc7SJiawei Lin    ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true)
3271f0e2dc7SJiawei Lin    ++ new WithNKBL1D(128)
3281f0e2dc7SJiawei Lin    ++ new BaseConfig(n)
329a1ea7f76SJiawei Lin)
330d5be5d19SJiawei Lin
331496c0adfSJiawei Linclass DefaultConfig(n: Int = 1) extends Config(
3320fbed464SJiawei Lin  new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6)
33359239bc9SJiawei Lin    ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true)
334d5be5d19SJiawei Lin    ++ new WithNKBL1D(128)
335d5be5d19SJiawei Lin    ++ new BaseConfig(n)
336d5be5d19SJiawei Lin)
337