xref: /XiangShan/src/main/scala/system/SoC.scala (revision f973ab00f36a43196f948e67b30d0eff5b65d055) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.DebugModule
23import freechips.rocketchip.amba.axi4.{AXI4Deinterleaver, AXI4Fragmenter, AXI4IdIndexer, AXI4MasterNode, AXI4MasterParameters, AXI4MasterPortParameters, AXI4SlaveNode, AXI4SlaveParameters, AXI4SlavePortParameters, AXI4ToTL, AXI4UserYanker}
24import freechips.rocketchip.devices.tilelink.{CLINT, CLINTParams, DevNullParams, PLICParams, TLError, TLPLIC}
25import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
26import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
27import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters}
28import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors}
29import freechips.rocketchip.tilelink.{BankBinder, TLBuffer, TLCacheCork, TLFIFOFixer, TLTempNode, TLToAXI4, TLWidthWidget, TLXbar}
30import huancun.debug.TLLogger
31import huancun.{CacheParameters, HCCacheParameters}
32import top.BusPerfMonitor
33
34case object SoCParamsKey extends Field[SoCParameters]
35
36case class SoCParameters
37(
38  cores: List[XSCoreParameters],
39  EnableILA: Boolean = false,
40  extIntrs: Int = 150,
41  L3NBanks: Int = 4,
42  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
43    name = "l3",
44    level = 3,
45    ways = 8,
46    sets = 2048 // 1MB per bank
47  ))
48){
49  val PAddrBits = cores.map(_.PAddrBits).reduce((x, y) => if(x > y) x else y)
50  // L3 configurations
51  val L3InnerBusWidth = 256
52  val L3BlockSize = 64
53  // on chip network configurations
54  val L3OuterBusWidth = 256
55}
56
57trait HasSoCParameter {
58  implicit val p: Parameters
59
60  val soc = p(SoCParamsKey)
61  val debugOpts = p(DebugOptionsKey)
62  val NumCores = soc.cores.size
63  val EnableILA = soc.EnableILA
64
65  // L3 configurations
66  val L3InnerBusWidth = soc.L3InnerBusWidth
67  val L3BlockSize = soc.L3BlockSize
68  val L3NBanks = soc.L3NBanks
69
70  // on chip network configurations
71  val L3OuterBusWidth = soc.L3OuterBusWidth
72
73  val NrExtIntr = soc.extIntrs
74}
75
76class ILABundle extends Bundle {}
77
78
79abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
80  val bankedNode = BankBinder(L3NBanks, L3BlockSize)
81  val peripheralXbar = TLXbar()
82  val l3_xbar = TLXbar()
83}
84
85// We adapt the following three traits from rocket-chip.
86// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
87trait HaveSlaveAXI4Port {
88  this: BaseSoC =>
89
90  val idBits = 14
91
92  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
93    Seq(AXI4MasterParameters(
94      name = "dma",
95      id = IdRange(0, 1 << idBits)
96    ))
97  )))
98  private val errorDevice = LazyModule(new TLError(
99    params = DevNullParams(
100      address = Seq(AddressSet(0x0, 0x7fffffffL)),
101      maxAtomic = 8,
102      maxTransfer = 64),
103    beatBytes = L3InnerBusWidth / 8
104  ))
105  private val error_xbar = TLXbar()
106
107  error_xbar :=
108    TLFIFOFixer() :=
109    TLWidthWidget(16) :=
110    AXI4ToTL() :=
111    AXI4UserYanker(Some(1)) :=
112    AXI4Fragmenter() :=
113    AXI4IdIndexer(1) :=
114    l3FrontendAXI4Node
115  errorDevice.node := error_xbar
116  l3_xbar :=
117    TLBuffer() :=
118    error_xbar
119
120  val dma = InModuleBody {
121    l3FrontendAXI4Node.makeIOs()
122  }
123}
124
125trait HaveAXI4MemPort {
126  this: BaseSoC =>
127  val device = new MemoryDevice
128  // 40-bit physical address
129  val memRange = AddressSet(0x00000000L, 0xffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
130  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
131    AXI4SlavePortParameters(
132      slaves = Seq(
133        AXI4SlaveParameters(
134          address = memRange,
135          regionType = RegionType.UNCACHED,
136          executable = true,
137          supportsRead = TransferSizes(1, L3BlockSize),
138          supportsWrite = TransferSizes(1, L3BlockSize),
139          interleavedId = Some(0),
140          resources = device.reg("mem")
141        )
142      ),
143      beatBytes = L3OuterBusWidth / 8
144    )
145  ))
146
147  val mem_xbar = TLXbar()
148  mem_xbar :=* TLBuffer() :=* TLCacheCork() :=* bankedNode
149  memAXI4SlaveNode :=
150    AXI4UserYanker() :=
151    AXI4Deinterleaver(L3BlockSize) :=
152    TLToAXI4() :=
153    TLWidthWidget(L3OuterBusWidth / 8) :=
154    mem_xbar
155
156  val memory = InModuleBody {
157    memAXI4SlaveNode.makeIOs()
158  }
159}
160
161trait HaveAXI4PeripheralPort { this: BaseSoC =>
162  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
163  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
164  val uartRange = AddressSet(0x40600000, 0xf)
165  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
166  val uartParams = AXI4SlaveParameters(
167    address = Seq(uartRange),
168    regionType = RegionType.UNCACHED,
169    supportsRead = TransferSizes(1, 8),
170    supportsWrite = TransferSizes(1, 8),
171    resources = uartDevice.reg
172  )
173  val peripheralRange = AddressSet(
174    0x0, 0x7fffffff
175  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
176  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
177    Seq(AXI4SlaveParameters(
178      address = peripheralRange,
179      regionType = RegionType.UNCACHED,
180      supportsRead = TransferSizes(1, 8),
181      supportsWrite = TransferSizes(1, 8),
182      interleavedId = Some(0)
183    ), uartParams),
184    beatBytes = 8
185  )))
186
187  peripheralNode :=
188    AXI4UserYanker() :=
189    AXI4Deinterleaver(8) :=
190    TLToAXI4() :=
191    peripheralXbar
192
193  val peripheral = InModuleBody {
194    peripheralNode.makeIOs()
195  }
196
197}
198
199class SoCMisc()(implicit p: Parameters) extends BaseSoC
200  with HaveAXI4MemPort
201  with HaveAXI4PeripheralPort
202  with HaveSlaveAXI4Port
203{
204  val peripheral_ports = Array.fill(NumCores) { TLTempNode() }
205  val core_to_l3_ports = Array.fill(NumCores) { TLTempNode() }
206
207  val l3_in = TLTempNode()
208  val l3_out = TLTempNode()
209  val l3_mem_pmu = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
210
211  l3_in :*= TLBuffer() :*= l3_xbar
212  bankedNode :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform) :*= l3_mem_pmu :*= l3_out
213
214  if(soc.L3CacheParamsOpt.isEmpty){
215    l3_out :*= l3_in
216  }
217
218  for(port <- peripheral_ports) {
219    peripheralXbar := port
220  }
221
222  for ((core_out, i) <- core_to_l3_ports.zipWithIndex){
223    l3_xbar :=* TLBuffer() :=* TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform) :=* core_out
224  }
225
226  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
227  clint.node := peripheralXbar
228
229  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
230    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
231    lazy val module = new LazyModuleImp(this){
232      val in = IO(Input(Vec(num, Bool())))
233      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
234    }
235  }
236
237  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
238  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
239
240  plic.intnode := plicSource.sourceNode
241  plic.node := peripheralXbar
242
243  val debugModule = LazyModule(new DebugModule(NumCores)(p))
244  debugModule.debug.node := peripheralXbar
245  debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
246    l3_xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node
247  }
248
249  lazy val module = new LazyModuleImp(this){
250
251    val debug_module_io = IO(chiselTypeOf(debugModule.module.io))
252    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
253
254    debugModule.module.io <> debug_module_io
255    plicSource.module.in := ext_intrs.asBools
256
257    val freq = 100
258    val cnt = RegInit(freq.U)
259    val tick = cnt === 0.U
260    cnt := Mux(tick, freq.U, cnt - 1.U)
261    clint.module.io.rtcTick := tick
262  }
263}
264