xref: /XiangShan/src/main/scala/system/SoC.scala (revision f1ae1cd3530691fae1969551077012bc9fd02c52) 
1package system
2
3import noop._
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6
7import chisel3._
8import chisel3.util._
9import chisel3.util.experimental.BoringUtils
10
11trait HasSoCParameter {
12  val EnableILA = false
13  val HasL2cache = true
14  val HasPrefetch = false
15}
16
17class ILABundle extends Bundle {
18  val WBUpc = UInt(32.W)
19  val WBUvalid = UInt(1.W)
20  val WBUrfWen = UInt(1.W)
21  val WBUrfDest = UInt(5.W)
22  val WBUrfData = UInt(64.W)
23  val InstrCnt = UInt(64.W)
24}
25
26class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
27  val io = IO(new Bundle{
28    val mem = new AXI4
29    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
30    val mtip = Input(Bool())
31    val meip = Input(Bool())
32    val ila = if (p.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
33  })
34
35  val noop = Module(new NOOP)
36
37	val cohMg = Module(new CoherenceManager)
38  val xbar = Module(new SimpleBusCrossbarNto1(2))
39  cohMg.io.in <> noop.io.imem.mem
40  noop.io.dmem.coh <> cohMg.io.out.coh
41  xbar.io.in(0) <> cohMg.io.out.mem
42  xbar.io.in(1) <> noop.io.dmem.mem
43
44	if (HasL2cache) {
45    val l2cacheOut = Wire(new SimpleBusC)
46    if (HasPrefetch) {
47			val prefetcher = Module(new Prefetcher)
48			prefetcher.io.in <> noop.io.prefetchReq
49			val l2cacheIn = Wire(new SimpleBusUC)
50			val l2cacheInReqArb = Module(new Arbiter(chiselTypeOf(noop.io.prefetchReq.bits), 2))
51			l2cacheInReqArb.io.in(0) <> xbar.io.out.req
52			l2cacheInReqArb.io.in(1) <> prefetcher.io.out
53			l2cacheIn.req <> l2cacheInReqArb.io.out
54			xbar.io.out.resp <> l2cacheIn.resp
55			l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
56		} else {
57			l2cacheOut <> Cache(in = xbar.io.out, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
58		}
59    io.mem <> l2cacheOut.mem.toAXI4()
60		l2cacheOut.coh.resp.ready := true.B
61		l2cacheOut.coh.req.valid := false.B
62		l2cacheOut.coh.req.bits := DontCare
63  } else {
64    io.mem <> xbar.io.out.toAXI4()
65  }
66
67	if (!HasPrefetch) {
68		noop.io.prefetchReq.ready := true.B
69	}
70
71  noop.io.imem.coh.resp.ready := true.B
72  noop.io.imem.coh.req.valid := false.B
73  noop.io.imem.coh.req.bits := DontCare
74
75  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
76  else io.mmio <> noop.io.mmio
77
78  val mtipSync = RegNext(RegNext(io.mtip))
79  val meipSync = RegNext(RegNext(io.meip))
80  BoringUtils.addSource(mtipSync, "mtip")
81  BoringUtils.addSource(meipSync, "meip")
82
83  // ILA
84  if (p.FPGAPlatform) {
85    def BoringUtilsConnect(sink: UInt, id: String) {
86      val temp = WireInit(0.U(64.W))
87      BoringUtils.addSink(temp, id)
88      sink := temp
89    }
90
91    val dummy = WireInit(0.U.asTypeOf(new ILABundle))
92    val ila = io.ila.getOrElse(dummy)
93    BoringUtilsConnect(ila.WBUpc      ,"ilaWBUpc")
94    BoringUtilsConnect(ila.WBUvalid   ,"ilaWBUvalid")
95    BoringUtilsConnect(ila.WBUrfWen   ,"ilaWBUrfWen")
96    BoringUtilsConnect(ila.WBUrfDest  ,"ilaWBUrfDest")
97    BoringUtilsConnect(ila.WBUrfData  ,"ilaWBUrfData")
98    BoringUtilsConnect(ila.InstrCnt   ,"ilaInstrCnt")
99  }
100}
101