xref: /XiangShan/src/main/scala/system/SoC.scala (revision d2d827d92f583d226d9c6b7f6172053c68db5920) 
1package system
2
3import noop.{NOOP, NOOPConfig, Cache, L2Cache, CacheConfig}
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6
7import chisel3._
8import chisel3.util._
9import chisel3.util.experimental.BoringUtils
10
11class NOOPSoC(implicit val p: NOOPConfig) extends Module {
12  val io = IO(new Bundle{
13    val mem = new AXI4
14    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
15    val mtip = Input(Bool())
16    val meip = Input(Bool())
17  })
18
19  val noop = Module(new NOOP)
20  val cohMg = Module(new CoherenceInterconnect)
21  cohMg.io.in(0) <> noop.io.imem
22  cohMg.io.in(1) <> noop.io.dmem
23
24
25	// add L2 Cache and Dcache Prefetcher
26	/*
27	val prefetcher = Module(new Prefetcher)
28	prefetcher.io.in <> noop.io.prefetchReq
29
30	val l2cacheIn = Wire(new SimpleBusUC)
31	val l2cacheInReqArb = Module(new Arbiter(chiselTypeOf(noop.io.prefetchReq.bits), 2))
32	l2cacheInReqArb.io.in(0) <> cohMg.io.out.req
33	l2cacheInReqArb.io.in(1) <> prefetcher.io.out
34	l2cacheIn.req <> l2cacheInReqArb.io.out
35	cohMg.io.out.resp <> l2cacheIn.resp
36
37	val mmioXbar = Module(new SimpleBusCrossbarNto1(2))
38
39	val l2cacheOut = Wire(new SimpleBusUC)
40	l2cacheOut <> Cache(in = l2cacheIn, mmio = mmioXbar.io.in(0), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
41	io.mem <> l2cacheOut.toAXI4()
42
43	mmioXbar.io.in(1) <> noop.io.mmio
44	if (p.FPGAPlatform) io.mmio <> mmioXbar.io.out.toAXI4Lite()
45  else io.mmio <> mmioXbar.io.out
46	*/
47
48	// add L2 Cache
49	/*
50	val mmioXbar = Module(new SimpleBusCrossbarNto1(2))
51
52	val l2cacheOut = Wire(new SimpleBusUC)
53	l2cacheOut <> Cache(in = cohMg.io.out, mmio = mmioXbar.io.in(0), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
54	io.mem <> l2cacheOut.toAXI4()
55
56	mmioXbar.io.in(1) <> noop.io.mmio
57	if (p.FPGAPlatform) io.mmio <> mmioXbar.io.out.toAXI4Lite()
58  else io.mmio <> mmioXbar.io.out
59	*/
60
61	// no L2 Cache
62
63	io.mem <> cohMg.io.out.toAXI4()
64
65  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
66  else io.mmio <> noop.io.mmio
67
68
69  val mtipSync = RegNext(RegNext(io.mtip))
70  val meipSync = RegNext(RegNext(io.meip))
71  BoringUtils.addSource(mtipSync, "mtip")
72  BoringUtils.addSource(meipSync, "meip")
73}
74