1package system 2 3import noop.{Cache, CacheConfig} 4import bus.axi4.{AXI4, AXI4Lite} 5import bus.simplebus._ 6import device.AXI4Timer 7import chisel3._ 8import chisel3.util._ 9import chisel3.util.experimental.BoringUtils 10import top.Parameters 11import xiangshan.XSCore 12 13 14case class SoCParameters 15( 16 EnableILA: Boolean = false, 17 HasL2Cache: Boolean = false, 18 HasPrefetch: Boolean = false 19) 20 21trait HasSoCParameter { 22 val soc = Parameters.get.socParameters 23 val env = Parameters.get.envParameters 24 val EnableILA = soc.EnableILA 25 val HasL2cache = soc.HasL2Cache 26 val HasPrefetch = soc.HasPrefetch 27} 28 29class ILABundle extends Bundle {} 30 31class XSSoc extends Module with HasSoCParameter { 32 val io = IO(new Bundle{ 33 val mem = new AXI4 34 val mmio = if (env.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC } 35 val frontend = Flipped(new AXI4) 36 val meip = Input(Bool()) 37 val ila = if (env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None 38 }) 39 40 val xsCore = Module(new XSCore) 41 val cohMg = Module(new CoherenceManager) 42 val xbar = Module(new SimpleBusCrossbarNto1(2)) 43 cohMg.io.in <> xsCore.io.imem.mem 44 xsCore.io.dmem.coh <> cohMg.io.out.coh 45 xbar.io.in(0) <> cohMg.io.out.mem 46 xbar.io.in(1) <> xsCore.io.dmem.mem 47 48 val axi2sb = Module(new AXI42SimpleBusConverter()) 49 axi2sb.io.in <> io.frontend 50 xsCore.io.frontend <> axi2sb.io.out 51 52 if (HasL2cache) { 53 val l2cacheOut = Wire(new SimpleBusC) 54 val l2cacheIn = if (HasPrefetch) { 55 val prefetcher = Module(new Prefetcher) 56 val l2cacheIn = Wire(new SimpleBusUC) 57 prefetcher.io.in <> xbar.io.out.req 58 l2cacheIn.req <> prefetcher.io.out 59 xbar.io.out.resp <> l2cacheIn.resp 60 l2cacheIn 61 } else xbar.io.out 62 val l2Empty = Wire(Bool()) 63 l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC) :: Nil, flush = "b00".U, empty = l2Empty, enable = true)( 64 CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2)) 65 io.mem <> l2cacheOut.mem.toAXI4() 66 l2cacheOut.coh.resp.ready := true.B 67 l2cacheOut.coh.req.valid := false.B 68 l2cacheOut.coh.req.bits := DontCare 69 } else { 70 io.mem <> xbar.io.out.toAXI4() 71 } 72 xsCore.io.imem.coh.resp.ready := true.B 73 xsCore.io.imem.coh.req.valid := false.B 74 xsCore.io.imem.coh.req.bits := DontCare 75 76 val addrSpace = List( 77 (0x40000000L, 0x40000000L), // external devices 78 (0x38000000L, 0x00010000L) // CLINT 79 ) 80 val mmioXbar = Module(new SimpleBusCrossbar1toN(addrSpace)) 81 mmioXbar.io.in <> xsCore.io.mmio 82 83 val extDev = mmioXbar.io.out(0) 84 val clint = Module(new AXI4Timer(sim = !env.FPGAPlatform)) 85 clint.io.in <> mmioXbar.io.out(1).toAXI4Lite() 86 if (env.FPGAPlatform) io.mmio <> extDev.toAXI4Lite() 87 else io.mmio <> extDev 88 89 val mtipSync = clint.io.extra.get.mtip 90 val meipSync = RegNext(RegNext(io.meip)) 91 BoringUtils.addSource(mtipSync, "mtip") 92 BoringUtils.addSource(meipSync, "meip") 93} 94