xref: /XiangShan/src/main/scala/system/SoC.scala (revision b5c2af596aad0311c0a46689b59edf5df8a6761c) 
1package system
2
3import noop._
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6
7import chisel3._
8import chisel3.util._
9import chisel3.util.experimental.BoringUtils
10
11trait HasILAParameter {
12  val enableILA = false
13}
14
15class ILABundle extends Bundle {
16  val WBUpc = UInt(32.W)
17  val WBUvalid = UInt(1.W)
18  val WBUrfWen = UInt(1.W)
19  val WBUrfDest = UInt(5.W)
20  val WBUrfData = UInt(64.W)
21  val InstrCnt = UInt(64.W)
22}
23
24class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasILAParameter {
25  val io = IO(new Bundle{
26    val mem = new AXI4
27    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
28    val mtip = Input(Bool())
29    val meip = Input(Bool())
30    val ila = if (p.FPGAPlatform && enableILA) Some(Output(new ILABundle)) else None
31  })
32
33  val noop = Module(new NOOP)
34
35	val cohMg = Module(new CoherenceManager)
36  val xbar = Module(new SimpleBusCrossbarNto1(2))
37  cohMg.io.in <> noop.io.imem.mem
38  noop.io.dmem.coh <> cohMg.io.out.coh
39  xbar.io.in(0) <> cohMg.io.out.mem
40  xbar.io.in(1) <> noop.io.dmem.mem
41
42	if (HasL2cache) {
43    val l2cacheOut = Wire(new SimpleBusC)
44    if (HasPrefetch) {
45			val prefetcher = Module(new Prefetcher)
46			prefetcher.io.in <> noop.io.prefetchReq
47			val l2cacheIn = Wire(new SimpleBusUC)
48			val l2cacheInReqArb = Module(new Arbiter(chiselTypeOf(noop.io.prefetchReq.bits), 2))
49			l2cacheInReqArb.io.in(0) <> xbar.io.out.req
50			l2cacheInReqArb.io.in(1) <> prefetcher.io.out
51			l2cacheIn.req <> l2cacheInReqArb.io.out
52			xbar.io.out.resp <> l2cacheIn.resp
53			l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
54		} else {
55			l2cacheOut <> Cache(in = xbar.io.out, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
56		}
57    io.mem <> l2cacheOut.mem.toAXI4()
58		l2cacheOut.coh.resp.ready := true.B
59		l2cacheOut.coh.req.valid := false.B
60		l2cacheOut.coh.req.bits := DontCare
61  } else {
62    io.mem <> xbar.io.out.toAXI4()
63  }
64
65	if (!HasPrefetch) {
66		noop.io.prefetchReq.ready := true.B
67	}
68
69  noop.io.imem.coh.resp.ready := true.B
70  noop.io.imem.coh.req.valid := false.B
71  noop.io.imem.coh.req.bits := DontCare
72
73  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
74  else io.mmio <> noop.io.mmio
75
76  val mtipSync = RegNext(RegNext(io.mtip))
77  val meipSync = RegNext(RegNext(io.meip))
78  BoringUtils.addSource(mtipSync, "mtip")
79  BoringUtils.addSource(meipSync, "meip")
80
81  // ILA
82  if (p.FPGAPlatform) {
83    def BoringUtilsConnect(sink: UInt, id: String) {
84      val temp = WireInit(0.U(64.W))
85      BoringUtils.addSink(temp, id)
86      sink := temp
87    }
88
89    val dummy = WireInit(0.U.asTypeOf(new ILABundle))
90    val ila = io.ila.getOrElse(dummy)
91    BoringUtilsConnect(ila.WBUpc      ,"ilaWBUpc")
92    BoringUtilsConnect(ila.WBUvalid   ,"ilaWBUvalid")
93    BoringUtilsConnect(ila.WBUrfWen   ,"ilaWBUrfWen")
94    BoringUtilsConnect(ila.WBUrfDest  ,"ilaWBUrfDest")
95    BoringUtilsConnect(ila.WBUrfData  ,"ilaWBUrfData")
96    BoringUtilsConnect(ila.InstrCnt   ,"ilaInstrCnt")
97  }
98}
99