xref: /XiangShan/src/main/scala/system/SoC.scala (revision 887862dbb8debde8ab099befc426493834a69ee7) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.tilelink._
25import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
26import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
27import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
28import freechips.rocketchip.tilelink._
29import freechips.rocketchip.util.AsyncQueueParams
30import huancun._
31import top.BusPerfMonitor
32import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
33import xiangshan.backend.fu.PMAConst
34import xiangshan.{DebugOptionsKey, XSTileKey}
35import coupledL2.EnableCHI
36import coupledL2.tl2chi.CHIIssue
37
38case object SoCParamsKey extends Field[SoCParameters]
39
40case class SoCParameters
41(
42  EnableILA: Boolean = false,
43  PAddrBits: Int = 48,
44  extIntrs: Int = 64,
45  L3NBanks: Int = 4,
46  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
47    name = "L3",
48    level = 3,
49    ways = 8,
50    sets = 2048 // 1MB per bank
51  )),
52  XSTopPrefix: Option[String] = None,
53  NodeIDWidthList: Map[String, Int] = Map(
54    "B" -> 7,
55    "E.b" -> 11
56  ),
57  NumHart: Int = 64,
58  NumIRFiles: Int = 7,
59  NumIRSrc: Int = 256,
60  UseXSNoCTop: Boolean = false,
61  IMSICUseTL: Boolean = false,
62  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 4, sync = 3)),
63  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(1))
64){
65  // L3 configurations
66  val L3InnerBusWidth = 256
67  val L3BlockSize = 64
68  // on chip network configurations
69  val L3OuterBusWidth = 256
70}
71
72trait HasSoCParameter {
73  implicit val p: Parameters
74
75  val soc = p(SoCParamsKey)
76  val debugOpts = p(DebugOptionsKey)
77  val tiles = p(XSTileKey)
78  val enableCHI = p(EnableCHI)
79  val issue = p(CHIIssue)
80
81  val NumCores = tiles.size
82  val EnableILA = soc.EnableILA
83
84  // L3 configurations
85  val L3InnerBusWidth = soc.L3InnerBusWidth
86  val L3BlockSize = soc.L3BlockSize
87  val L3NBanks = soc.L3NBanks
88
89  // on chip network configurations
90  val L3OuterBusWidth = soc.L3OuterBusWidth
91
92  val NrExtIntr = soc.extIntrs
93
94  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
95
96  val NumIRSrc = soc.NumIRSrc
97
98  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
99    soc.EnableCHIAsyncBridge else None
100  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
101}
102
103class ILABundle extends Bundle {}
104
105
106abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
107  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
108  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
109  val l3_xbar = Option.when(!enableCHI)(TLXbar())
110  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
111
112  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
113}
114
115// We adapt the following three traits from rocket-chip.
116// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
117trait HaveSlaveAXI4Port {
118  this: BaseSoC =>
119
120  val idBits = 14
121
122  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
123    Seq(AXI4MasterParameters(
124      name = "dma",
125      id = IdRange(0, 1 << idBits)
126    ))
127  )))
128
129  if (l3_xbar.isDefined) {
130    val errorDevice = LazyModule(new TLError(
131      params = DevNullParams(
132        address = Seq(AddressSet(0x0, 0x7fffffffL)),
133        maxAtomic = 8,
134        maxTransfer = 64),
135      beatBytes = L3InnerBusWidth / 8
136    ))
137    errorDevice.node :=
138      l3_xbar.get :=
139      TLFIFOFixer() :=
140      TLWidthWidget(32) :=
141      AXI4ToTL() :=
142      AXI4UserYanker(Some(1)) :=
143      AXI4Fragmenter() :=
144      AXI4Buffer() :=
145      AXI4Buffer() :=
146      AXI4IdIndexer(1) :=
147      l3FrontendAXI4Node
148  }
149
150  val dma = InModuleBody {
151    l3FrontendAXI4Node.makeIOs()
152  }
153}
154
155trait HaveAXI4MemPort {
156  this: BaseSoC =>
157  val device = new MemoryDevice
158  // 48-bit physical address
159  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
160  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
161    AXI4SlavePortParameters(
162      slaves = Seq(
163        AXI4SlaveParameters(
164          address = memRange,
165          regionType = RegionType.UNCACHED,
166          executable = true,
167          supportsRead = TransferSizes(1, L3BlockSize),
168          supportsWrite = TransferSizes(1, L3BlockSize),
169          interleavedId = Some(0),
170          resources = device.reg("mem")
171        )
172      ),
173      beatBytes = L3OuterBusWidth / 8,
174      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
175    )
176  ))
177
178  val mem_xbar = TLXbar()
179  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
180  val axi4mem_node = AXI4IdentityNode()
181
182  if (enableCHI) {
183    axi4mem_node :=
184      soc_xbar.get
185  } else {
186    mem_xbar :=*
187      TLBuffer.chainNode(2) :=
188      TLCacheCork() :=
189      l3_mem_pmu :=
190      TLClientsMerger() :=
191      TLXbar() :=*
192      bankedNode.get
193
194    mem_xbar :=
195      TLWidthWidget(8) :=
196      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
197      peripheralXbar.get
198
199    axi4mem_node :=
200      TLToAXI4() :=
201      TLSourceShrinker(64) :=
202      TLWidthWidget(L3OuterBusWidth / 8) :=
203      TLBuffer.chainNode(2) :=
204      mem_xbar
205  }
206
207  memAXI4SlaveNode :=
208    AXI4Buffer() :=
209    AXI4Buffer() :=
210    AXI4Buffer() :=
211    AXI4IdIndexer(idBits = 14) :=
212    AXI4UserYanker() :=
213    AXI4Deinterleaver(L3BlockSize) :=
214    axi4mem_node
215
216  val memory = InModuleBody {
217    memAXI4SlaveNode.makeIOs()
218  }
219}
220
221trait HaveAXI4PeripheralPort { this: BaseSoC =>
222  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
223  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
224  val uartRange = AddressSet(0x40600000, 0x3f)
225  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
226  val uartParams = AXI4SlaveParameters(
227    address = Seq(uartRange),
228    regionType = RegionType.UNCACHED,
229    supportsRead = TransferSizes(1, 32),
230    supportsWrite = TransferSizes(1, 32),
231    resources = uartDevice.reg
232  )
233  val peripheralRange = AddressSet(
234    0x0, 0x7fffffff
235  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
236  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
237    Seq(AXI4SlaveParameters(
238      address = peripheralRange,
239      regionType = RegionType.UNCACHED,
240      supportsRead = TransferSizes(1, 32),
241      supportsWrite = TransferSizes(1, 32),
242      interleavedId = Some(0)
243    ), uartParams),
244    beatBytes = 8
245  )))
246
247  val axi4peripheral_node = AXI4IdentityNode()
248  val error_xbar = Option.when(enableCHI)(TLXbar())
249
250  peripheralNode :=
251    AXI4UserYanker() :=
252    AXI4IdIndexer(idBits = 2) :=
253    AXI4Buffer() :=
254    AXI4Buffer() :=
255    AXI4Buffer() :=
256    AXI4Buffer() :=
257    AXI4UserYanker() :=
258    // AXI4Deinterleaver(8) :=
259    axi4peripheral_node
260
261  if (enableCHI) {
262    val error = LazyModule(new TLError(
263      params = DevNullParams(
264        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
265        maxAtomic = 8,
266        maxTransfer = 64),
267      beatBytes = 8
268    ))
269    error.node := error_xbar.get
270    axi4peripheral_node :=
271      AXI4Deinterleaver(8) :=
272      TLToAXI4() :=
273      error_xbar.get :=
274      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
275      TLFIFOFixer() :=
276      TLWidthWidget(L3OuterBusWidth / 8) :=
277      AXI4ToTL() :=
278      AXI4UserYanker() :=
279      soc_xbar.get
280  } else {
281    axi4peripheral_node :=
282      AXI4Deinterleaver(8) :=
283      TLToAXI4() :=
284      TLBuffer.chainNode(3) :=
285      peripheralXbar.get
286  }
287
288  val peripheral = InModuleBody {
289    peripheralNode.makeIOs()
290  }
291
292}
293
294class MemMisc()(implicit p: Parameters) extends BaseSoC
295  with HaveAXI4MemPort
296  with PMAConst
297  with HaveAXI4PeripheralPort
298{
299
300  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
301  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
302
303  val l3_in = TLTempNode()
304  val l3_out = TLTempNode()
305
306  val device_xbar = Option.when(enableCHI)(TLXbar())
307  device_xbar.foreach(_ := error_xbar.get)
308
309  if (l3_banked_xbar.isDefined) {
310    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
311    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
312  }
313  bankedNode match {
314    case Some(bankBinder) =>
315      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
316    case None =>
317  }
318
319  if(soc.L3CacheParamsOpt.isEmpty){
320    l3_out :*= l3_in
321  }
322
323  if (!enableCHI) {
324    for (port <- peripheral_ports.get) {
325      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
326    }
327  }
328
329  core_to_l3_ports.foreach { case _ =>
330    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
331      l3_banked_xbar.get :=*
332        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
333        TLBuffer() :=
334        core_out
335    }
336  }
337
338  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
339  if (enableCHI) { clint.node := device_xbar.get }
340  else { clint.node := peripheralXbar.get }
341
342  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
343    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
344    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
345      val in = IO(Input(Vec(num, Bool())))
346      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
347    }
348    lazy val module = new IntSourceNodeToModuleImp(this)
349  }
350
351  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
352  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
353
354  plic.intnode := plicSource.sourceNode
355  if (enableCHI) { plic.node := device_xbar.get }
356  else { plic.node := peripheralXbar.get }
357
358  val pll_node = TLRegisterNode(
359    address = Seq(AddressSet(0x3a000000L, 0xfff)),
360    device = new SimpleDevice("pll_ctrl", Seq()),
361    beatBytes = 8,
362    concurrency = 1
363  )
364  if (enableCHI) { pll_node := device_xbar.get }
365  else { pll_node := peripheralXbar.get }
366
367  val debugModule = LazyModule(new DebugModule(NumCores)(p))
368  if (enableCHI) {
369    debugModule.debug.node := device_xbar.get
370    // TODO: l3_xbar
371    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
372      error_xbar.get := sb2tl.node
373    }
374  } else {
375    debugModule.debug.node := peripheralXbar.get
376    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
377      l3_xbar.get := TLBuffer() := sb2tl.node
378    }
379  }
380
381  val pma = LazyModule(new TLPMA)
382  if (enableCHI) {
383    pma.node := TLBuffer.chainNode(4) := device_xbar.get
384  } else {
385    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
386  }
387
388  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
389
390    val debug_module_io = IO(new debugModule.DebugModuleIO)
391    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
392    val rtc_clock = IO(Input(Bool()))
393    val pll0_lock = IO(Input(Bool()))
394    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
395    val cacheable_check = IO(new TLPMAIO)
396    val clintTime = IO(Output(ValidIO(UInt(64.W))))
397
398    debugModule.module.io <> debug_module_io
399
400    // sync external interrupts
401    require(plicSource.module.in.length == ext_intrs.getWidth)
402    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
403      val ext_intr_sync = RegInit(0.U(3.W))
404      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
405      plic_in := ext_intr_sync(2)
406    }
407
408    pma.module.io <> cacheable_check
409
410    // positive edge sampling of the lower-speed rtc_clock
411    val rtcTick = RegInit(0.U(3.W))
412    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
413    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
414
415    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
416    val pll_lock = RegNext(next = pll0_lock, init = false.B)
417
418    clintTime := clint.module.io.time
419
420    pll0_ctrl <> VecInit(pll_ctrl_regs)
421
422    pll_node.regmap(
423      0x000 -> RegFieldGroup(
424        "Pll", Some("PLL ctrl regs"),
425        pll_ctrl_regs.zipWithIndex.map{
426          case (r, i) => RegField(32, r, RegFieldDesc(
427            s"PLL_ctrl_$i",
428            desc = s"PLL ctrl register #$i"
429          ))
430        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
431          "PLL_lock",
432          "PLL lock register"
433        ))
434      )
435    )
436  }
437
438  lazy val module = new SoCMiscImp(this)
439}
440
441class SoCMisc()(implicit p: Parameters) extends MemMisc
442  with HaveSlaveAXI4Port
443
444