xref: /XiangShan/src/main/scala/system/SoC.scala (revision 8656be216543573dfa8830aeb6491f4f531795f3) 
1package system
2
3import noop._
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6
7import chisel3._
8import chisel3.util._
9import chisel3.util.experimental.BoringUtils
10
11trait HasSoCParameter {
12  val EnableILA = false
13  val HasL2cache = true
14  val HasPrefetch = false
15}
16
17class ILABundle extends Bundle {
18  val WBUpc = UInt(32.W)
19  val WBUvalid = UInt(1.W)
20  val WBUrfWen = UInt(1.W)
21  val WBUrfDest = UInt(5.W)
22  val WBUrfData = UInt(64.W)
23  val InstrCnt = UInt(64.W)
24}
25
26class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
27  val io = IO(new Bundle{
28    val mem = new AXI4
29    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
30    val frontend = Flipped(new AXI4)
31    val mtip = Input(Bool())
32    val meip = Input(Bool())
33    val ila = if (p.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
34  })
35
36  val noop = Module(new NOOP)
37  val cohMg = Module(new CoherenceManager)
38  val xbar = Module(new SimpleBusCrossbarNto1(2))
39  cohMg.io.in <> noop.io.imem.mem
40  noop.io.dmem.coh <> cohMg.io.out.coh
41  xbar.io.in(0) <> cohMg.io.out.mem
42  xbar.io.in(1) <> noop.io.dmem.mem
43
44  val axi2sb = Module(new AXI42SimpleBusConverter())
45  axi2sb.io.in <> io.frontend
46  noop.io.frontend <> axi2sb.io.out
47
48  if (HasL2cache) {
49    val l2cacheOut = Wire(new SimpleBusC)
50    val l2cacheIn = if (HasPrefetch) {
51      val prefetcher = Module(new Prefetcher)
52      prefetcher.io.in <> noop.io.prefetchReq
53      val l2cacheIn = Wire(new SimpleBusUC)
54      val l2cacheInReqArb = Module(new Arbiter(chiselTypeOf(noop.io.prefetchReq.bits), 2))
55      l2cacheInReqArb.io.in(0) <> xbar.io.out.req
56      l2cacheInReqArb.io.in(1) <> prefetcher.io.out
57      l2cacheIn.req <> l2cacheInReqArb.io.out
58      xbar.io.out.resp <> l2cacheIn.resp
59      l2cacheIn
60    } else xbar.io.out
61    l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC) :: Nil, flush = "b00".U, enable = true)(
62      CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
63    io.mem <> l2cacheOut.mem.toAXI4()
64    l2cacheOut.coh.resp.ready := true.B
65    l2cacheOut.coh.req.valid := false.B
66    l2cacheOut.coh.req.bits := DontCare
67  } else {
68    io.mem <> xbar.io.out.toAXI4()
69  }
70
71  if (!HasPrefetch) {
72    noop.io.prefetchReq.ready := true.B
73  }
74
75  noop.io.imem.coh.resp.ready := true.B
76  noop.io.imem.coh.req.valid := false.B
77  noop.io.imem.coh.req.bits := DontCare
78
79  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
80  else io.mmio <> noop.io.mmio
81
82  val mtipSync = RegNext(RegNext(io.mtip))
83  val meipSync = RegNext(RegNext(io.meip))
84  BoringUtils.addSource(mtipSync, "mtip")
85  BoringUtils.addSource(meipSync, "meip")
86
87  // ILA
88  if (p.FPGAPlatform) {
89    def BoringUtilsConnect(sink: UInt, id: String) {
90      val temp = WireInit(0.U(64.W))
91      BoringUtils.addSink(temp, id)
92      sink := temp
93    }
94
95    val dummy = WireInit(0.U.asTypeOf(new ILABundle))
96    val ila = io.ila.getOrElse(dummy)
97    BoringUtilsConnect(ila.WBUpc      ,"ilaWBUpc")
98    BoringUtilsConnect(ila.WBUvalid   ,"ilaWBUvalid")
99    BoringUtilsConnect(ila.WBUrfWen   ,"ilaWBUrfWen")
100    BoringUtilsConnect(ila.WBUrfDest  ,"ilaWBUrfDest")
101    BoringUtilsConnect(ila.WBUrfData  ,"ilaWBUrfData")
102    BoringUtilsConnect(ila.InstrCnt   ,"ilaInstrCnt")
103  }
104}
105