1package system 2 3import noop.{Cache, CacheConfig} 4import bus.axi4.{AXI4, AXI4Lite, AXI4ToAXI4Lite} 5import bus.simplebus._ 6import bus.tilelink.{NaiveTL1toN, NaiveTLToAXI4, TLCached} 7import device.AXI4Timer 8import chisel3._ 9import chisel3.util._ 10import chisel3.util.experimental.BoringUtils 11import top.Parameters 12import xiangshan.{HasXSParameter, XSCore} 13 14 15case class SoCParameters 16( 17 EnableILA: Boolean = false, 18 HasL2Cache: Boolean = false, 19 HasPrefetch: Boolean = false 20) 21 22trait HasSoCParameter extends HasXSParameter{ 23 val soc = Parameters.get.socParameters 24 val EnableILA = soc.EnableILA 25 val HasL2cache = soc.HasL2Cache 26 val HasPrefetch = soc.HasPrefetch 27} 28 29class ILABundle extends Bundle {} 30 31class XSSoc extends Module with HasSoCParameter { 32 val io = IO(new Bundle{ 33 val mem = new TLCached(l1BusParams) 34 val mmio = new TLCached(l1BusParams) 35 val frontend = Flipped(new AXI4) //TODO: do we need it ? 36 val meip = Input(Bool()) 37 val ila = if (env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None 38 }) 39 40 val xsCore = Module(new XSCore) 41 42 io.frontend <> DontCare 43 44 io.mem <> xsCore.io.mem 45 46 val addrSpace = List( 47 (0x40000000L, 0x40000000L), // external devices 48 (0x38000000L, 0x00010000L) // CLINT 49 ) 50 val mmioXbar = Module(new NaiveTL1toN(addrSpace, xsCore.io.mem.params)) 51 mmioXbar.io.in <> xsCore.io.mmio 52 53 val extDev = mmioXbar.io.out(0) 54 val clint = Module(new AXI4Timer(sim = !env.FPGAPlatform)) 55 clint.io.in <> AXI4ToAXI4Lite(NaiveTLToAXI4(mmioXbar.io.out(1))) 56 57 io.mmio <> extDev 58 59 val mtipSync = clint.io.extra.get.mtip 60 val meipSync = RegNext(RegNext(io.meip)) 61 ExcitingUtils.addSource(mtipSync, "mtip") 62 ExcitingUtils.addSource(meipSync, "meip") 63} 64